Dual-Sided Die Package Routing and Thermal Management
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Solution Overview
Problem
Die-on-die stacking in semiconductor devices poses challenges for routing electrical connections and requires effective thermal management, particularly in high-performance devices like CPUs, where heat needs to be efficiently removed.
Innovation Solution
The configuration segregates system-level connections such as power and logic I/O contacts on opposite sides of a die, utilizing through-silicon vias, flip chip configurations, and thermal solutions like integrated heat spreaders and micro-channel cooling to manage heat dissipation, with 3D voltage regulators and heat exchangers integrated into the package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If die-on-die stacking is used to increase device functionality, then device performance and integration are improved, but routing of electrical connections becomes more complex and difficult
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by utilizing through-silicon vias (TSVs) that extend vertically through the die stack. This allows electrical connections to be established in the vertical dimension rather than requiring complex lateral routing paths, thereby resolving the routing complexity issue while maintaining the performance benefits of die stacking.
Solution Approach 2:
The patent introduces an interposer substrate as an intermediary component between stacked dies. This interposer provides a centralized routing layer that simplifies electrical connections by acting as a mediator that distributes signals to multiple dies, thereby reducing the overall routing complexity of the stacked configuration.
2Power
If high-performance devices are used to increase processing power, then device capability is improved, but heat generation increases requiring advanced thermal management
Solution Approach 1:
The patent merges the thermal management function with the electrical interconnection structure by integrating heat spreaders and thermal vias into the same TSV and interposer infrastructure. This combination allows simultaneous electrical signaling and heat dissipation through shared vertical pathways, effectively managing thermal loads in high-performance devices.
Solution Approach 2:
The patent employs liquid cooling channels integrated into the substrate and interposer structures, utilizing fluid flow to actively remove heat from the device. This hydraulic cooling system efficiently transports thermal energy away from high-power regions, enabling sustained high-performance operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient thermal management and reliable electrical connectivity, enhancing the performance and reliability of high-performance semiconductor devices by decoupling power and logic connections and integrating advanced cooling mechanisms within the package.
Implementation Method 1
coupled to the second side of the die. In one embodiment, the die includes logic input/output contact points on a device side of the die and power contact points on a back side of the die
Implementation Method 2
thermal solutions like integrated heat spreaders and micro-channel cooling to manage heat dissipation
Implementation Method 3
micro-channel cooling to manage heat dissipation
Implementation Method 4
flip chip configurations
Data Source
AI summary
An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.