Dual-Sided Peripheral Circuit Layout for Smaller 3D Memory Chips
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Solution Overview
Problem
Existing 3-dimensional nonvolatile memory devices face challenges in achieving lightness, thinness, simplification, and high integration due to limitations in circuit layout and connectivity between cell and peripheral areas.
Innovation Solution
A semiconductor device design featuring a cell area with gate electrodes, channel structures, and contact plugs, along with peripheral circuit areas on both sides of a substrate, connected through through electrodes, enabling a chip-to-chip structure for enhanced connectivity and reduced horizontal chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If peripheral circuit areas are placed only on one side of the substrate, then the layout is simpler, but the chip size cannot be minimized and integration density is reduced
Solution Approach 1:
The patent applies dimensionality change by placing peripheral circuit areas on both the front surface and back surface of the substrate, transitioning from a single-sided (2D) layout to a dual-sided (3D) configuration. This allows the chip size to be minimized while distributing circuit complexity across different spatial dimensions, with through-substrate vias providing vertical connectivity between the two surfaces.
2Ease of operation
If through electrodes are used to connect peripheral circuit areas on both sides of the substrate, then wiring interconnections are improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the wiring interconnection function into multiple components: bonding pads on the front surface, through-substrate vias penetrating the substrate, and corresponding pads on the back surface. This segmentation allows each component to be optimized independently while collectively achieving improved wiring interconnection efficiency, though it does increase manufacturing process complexity due to the need for precise via alignment and multi-step fabrication.
3Area of stationary object
If horizontal chip size is reduced for miniaturization, then integration density increases, but connectivity between cell and peripheral areas becomes more difficult
Solution Approach 1:
The patent resolves the connectivity challenge in miniaturized chips by utilizing the vertical dimension through through-substrate vias. These vias provide direct vertical pathways for signal transmission between the cell area on the front surface and peripheral circuit areas on the back surface, eliminating the need for lengthy horizontal interconnections and maintaining high connectivity efficiency despite reduced chip footprint.
Data Source
AI summary
A semiconductor device including a cell area including a first substrate, gate electrodes on the first substrate, a channel structure extending through the gate electrodes, cell contact plugs, a through contact plug, and first bonding pads, the first peripheral circuit area including second bonding pads on the first bonding pads; a second peripheral circuit area connected to the first peripheral circuit area; and a second substrate between the first peripheral circuit area and the second peripheral circuit area, the second substrate including a first surface in the first peripheral circuit area and a second surface in the second peripheral circuit area, wherein the second peripheral circuit area includes a device on the second surface, and a through electrode extending vertically through the second substrate and connected to the first peripheral circuit area.