Dual-Sided Memory Module Channel Alignment
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Solution Overview
Problem
Current memory modules face challenges in scaling memory beyond 32 GB without significant performance trade-offs, particularly due to increased capacitive loading and speed inversion, and manufacturing complexities with high die counts.
Innovation Solution
The implementation of memory packages with a dual-sided configuration, featuring a first terminal section with more electrically functional terminals and signal terminals, and a second terminal section with fewer signal terminals, allowing for increased memory density up to 64 GB by leveraging 8 Gb die memory and adjusting die density and bank control, while maintaining compatibility with existing manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased beyond 32 GB by adding more die, then memory capacity is improved, but capacitive loading increases and speed degrades
Solution Approach 1:
The memory module is divided into multiple independent memory packages (e.g., four first packages and four second packages), each operating as a separate channel. This segmentation allows each package to maintain lower capacitive loading and higher speed while the aggregate provides increased memory capacity beyond 32 GB.
Solution Approach 2:
The patent transitions from increasing capacity within a single package to expanding capacity across multiple packages arranged in channels and ranks. By adding the dimension of multiple packages per channel and multiple channels per module, the system achieves higher capacity without compromising the speed of individual packages.
2Quantity of substance
If die count is increased to achieve higher memory density, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of using a small number of high-density packages, the patent uses a larger number of lower-density packages (each with 4 ranks and single channel). This segmentation simplifies manufacturing by using standardized packages that are easier to produce and assemble, while achieving the same or greater total capacity through parallel configuration.
Solution Approach 2:
The patent changes the architectural parameters from high die count per package to multiple packages with standardized die counts. Each package uses a manageable number of die (e.g., 8 Gb die), but the overall module achieves high density through the combination of multiple packages, channels, and ranks, thereby reducing individual package manufacturing complexity.
3Device complexity
If single channel architecture is used, then device complexity is reduced, but productivity and memory bandwidth are limited
Solution Approach 1:
The patent combines multiple single-channel packages into multi-channel modules. By merging four first packages and four second packages into a unified memory module with multiple channels, the system achieves high memory bandwidth and productivity while keeping each individual package relatively simple with single-channel architecture.
Data Source
AI summary
Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.