Dual-Sided Semiconductor Stacking for Integration Density
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Solution Overview
Problem
Conventional 3D IC stacking techniques only allow for stacking wafers and/or dies on one side of a base substrate/wafer, limiting the integration density and performance improvements in semiconductor structures.
Innovation Solution
A method for manufacturing semiconductor structures by bonding semiconductor workpieces on both sides of a base substrate, using fusion bonding, hybrid bonding, and dielectric materials, with conductive vias and metal pads to connect microelectronic elements across multiple layers, enabling vertical interconnects and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 3D IC stacking techniques are used, then wafer/die stacking is enabled, but stacking is limited to one side of the base substrate
Solution Approach 1:
The patent transitions from conventional single-sided stacking to dual-sided stacking by utilizing both sides of the base substrate for wafer/die stacking. This dimensional change in the stacking configuration allows integration of multiple workpieces on opposite sides of the substrate, effectively doubling the potential integration density without increasing the footprint area.
2Productivity
If wafer/die stacking is implemented, then integration density increases, but the number of stacking positions is limited
Solution Approach 1:
The invention utilizes the third dimension (vertical stacking) on both sides of the substrate, transforming the limited two-dimensional substrate surface into a four-sided stacking platform. This allows maximum area utilization by distributing workpieces across all available surfaces of the substrate.
3Productivity
If dual-sided stacking is implemented, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary bonding actions by first bonding workpieces to both sides of the substrate before performing thinning operations. This sequence of operations simplifies the overall manufacturing process by establishing the stacking configuration early, then reducing the total thickness to achieve the desired form factor without complicating the bonding process.
Solution Approach 2:
The invention changes the thickness parameter of the substrate and workpieces through controlled thinning operations after bonding. This parameter change allows the structure to transition from a thick bonded assembly to a thin integrated package, making dual-sided stacking manufacturable with standard thinning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for enhanced performance and reduced power consumption by increasing integration density and enabling the stacking of semiconductor workpieces on both sides of the substrate, resulting in improved semiconductor structures with higher interconnect density and reduced form factor.
Implementation Method 1
bonding semiconductor workpieces on both sides of a base substrate/wafer using fusion bonding, hybrid bonding
Implementation Method 2
bonding semiconductor workpieces on both sides of a base substrate/wafer using fusion bonding, hybrid bonding
Data Source
AI summary
A semiconductor structure includes: a first semiconductor workpiece; a second semiconductor workpiece, bonded to a first surface of the first semiconductor workpiece, wherein the second semiconductor workpiece includes two adjacent semiconductor dies; a dielectric material, disposed between the two adjacent semiconductor dies; a first electrically conductive via, formed in the dielectric material and extended to electrically connect the first semiconductor workpiece; a third semiconductor workpiece, bonded to a second surface of the first semiconductor workpiece, the second surface being opposite to the first surface; and a second electrically conductive via, extended into the first semiconductor workpiece and substantially aligned with the first electrically conductive via such that the first electrically conductive via connects the second electrically conductive via.