Dual-Silicide Gate Electrode Uniformity

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Solution Overview

Problem

The existing gate electrode structures in field-effect transistors (FETs) often have non-uniform silicide formation at the gate dielectric interface, leading to inconsistent threshold voltage and higher leakage current due to incomplete silicidation, which can damage the gate oxide and affect device functionality.

Innovation Solution

A dual-silicide gate electrode structure is implemented, with a gate interface silicide formed by depositing a layer containing silicide retardation species underneath the metal/silicon layers, allowing for controlled silicide formation at a higher temperature or longer heat cycle, resulting in a fully silicided gate with a smooth and uniform interface with the gate dielectric.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thick silicon layer is used to form the silicide gate electrode, then high conductivity is achieved, but non-uniform silicide formation occurs at the gate dielectric interface

Engineering Contradiction:

ImproveconductivityVSAvoiduniformity of silicide formation

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate electrode is segmented into two distinct silicide regions: a gate interface silicide portion adjacent to the gate dielectric and a bulk gate silicide portion. This segmentation allows each region to be optimized independently - the interface region for uniformity and the bulk region for conductivity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different silicide compositions are used at different locations within the gate electrode. The gate interface silicide has a composition optimized for uniform formation and adhesion to the gate dielectric, while the bulk gate silicide has a composition optimized for high conductivity. This local quality differentiation resolves the contradiction between uniformity and conductivity.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If conventional silicidation processing is used, then processing simplicity is maintained, but silicide penetration into the gate dielectric occurs

Engineering Contradiction:

Improveprocessing simplicityVSAvoidsilicide penetration into gate dielectric

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

A silicide prevention layer is deposited between the gate electrode and gate dielectric before silicidation processing. This layer preemptively blocks silicide penetration into the gate dielectric during conventional high-temperature silicidation processing, allowing simple processing to produce a protected structure.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The silicide prevention layer acts as an intermediary barrier between the gate electrode and gate dielectric. It prevents direct interaction and penetration while allowing the conventional silicidation process to proceed, thus maintaining processing simplicity while eliminating the harmful penetration effect.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If full silicidation is not achieved at the gate dielectric-gate electrode interface, then processing time is reduced, but threshold voltage becomes inconsistent

Engineering Contradiction:

Improveprocessing timeVSAvoidthreshold voltage consistency

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The gate interface silicide is formed first with optimized conditions for uniform formation and adhesion to the gate dielectric. This preliminary action ensures a solid foundation before the bulk silicidation proceeds, guaranteeing threshold voltage consistency even when total processing time is reduced.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The silicidation process is divided into periodic stages: first forming the gate interface silicide under controlled conditions, then forming the bulk gate silicide. This periodic action ensures each stage achieves its specific objective, maintaining threshold voltage consistency while optimizing overall processing time.

Inventive Principle:

Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides a uniform threshold voltage, reduces gate leakage current, improves reliability, and enhances the operational speed and consistency of FETs by preventing silicide penetration into the gate dielectric and ensuring complete silicidation.

Implementation Method 1

The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed

Methodology Applied

Scientific EffectSilicide formation retardation:

Implementation Method 2

The wafer is heated so that the metal layer combines with the silicon to form a silicide gate electrode

Methodology Applied

Scientific EffectSilicidation:

Data Source

PatentUS7429526B1Method of forming silicide gate with interlayer

Publication Date: 2008.09.30 XILINX INC

AI summary

A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.