Dual Strained CMOS Channel Formation via Thermal Oxidation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional methods face challenges in effectively combining semiconductor layers with compressive and tensile strains on the same wafer, which is necessary for enhancing both p-channel and n-channel FET performance.

Innovation Solution

A method involving the formation of a tensile strained layer followed by epitaxial layers and thermal oxidation processes to create both compressive and tensile strained layers on the same wafer, allowing for the formation of both p-channel and n-channel FETs using the same process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to form semiconductor layers with compressive and tensile strains on the same wafer, then the manufacturing process becomes complex and difficult to control, but the carrier mobility improvement is achieved

Engineering Contradiction:
Improvestrain control precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the semiconductor layer formation into distinct regions: a first semiconductor layer with compressive strain for PFETs and a second semiconductor layer with tensile strain for NFETs. This segmentation allows each layer to be independently formed with controlled strain characteristics, avoiding the complexity of simultaneously controlling both strains in a single layer while still achieving carrier mobility improvement in both device types on the same wafer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by creating different strain conditions in different spatial locations on the wafer. The compressive strain is localized to the first semiconductor layer region where PFETs are formed, while tensile strain is localized to the second semiconductor layer region where NFETs are formed. This local differentiation enables precise strain control for each device type without requiring complex global process control.

Inventive Principle:
Principle #3Local quality

2Device complexity

If a single semiconductor layer is used for both p-channel and n-channel FETs, then the process is simpler, but carrier mobility cannot be optimized for both device types

Engineering Contradiction:
Improveprocess simplicityVSAvoidcarrier mobility performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the semiconductor structure into two separate layers: a first semiconductor layer with compressive strain optimized for p-channel FETs and a second semiconductor layer with tensile strain optimized for n-channel FETs. This segmentation enables independent optimization of carrier mobility for each device type while maintaining a relatively simple dual-layer process structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the strain parameter (compressive vs. tensile) between the first and second semiconductor layers to optimize carrier mobility for different device types. By controlling the strain parameter differently in each layer, the patent achieves high-performance PFETs and NFETs on the same wafer without requiring complex multi-step processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the simultaneous formation of p-channel and n-channel FETs on a single wafer with improved carrier mobility, enhancing device performance by leveraging strain engineering techniques.

Implementation Method 1

performing a thermal oxidation process, such that the upper epitaxial layer is converted to an oxide

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

thermal condensation causes a portion of the epitaxial layer below to become a compressive strained layer

Methodology Applied
Scientific EffectThermal condensation: Condensation

Data Source

PatentUS10049945B2Forming a CMOS with dual strained channels
Publication Date: 2018.08.14 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10049945B2 patent drawing
  • US10049945B2 patent drawing
  • US10049945B2 patent drawing

AI summary

The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.