Dual TiN pFET Work Metal Stack for NBTI Mitigation
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Solution Overview
Problem
High-temperature titanium nitride (TiN) derived from TiCl4 precursors can etch high-k layers and enhance negative-bias temperature instability (NBTI) in pFETs, leading to reduced device reliability and breakdown voltage.
Innovation Solution
A two-layer TiN stack is used, with a low-temperature first TiN layer rich in chlorine and a high-temperature second TiN layer, where the first TiN layer is incorporated into the high-k layer to mitigate NBTI and maintain high-k thickness, thereby improving device reliability and reducing gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature TiN is used as pFET work function gate stack, then gate resistance is reduced, but high-k layer etching occurs and NBTI is enhanced leading to reduced device reliability
Solution Approach 1:
The patent divides the work function gate stack into multiple layers: a first TiN layer deposited at low temperature (300-400°C) and a second TiN layer deposited at high temperature (400-600°C). This segmentation allows the first layer to protect the high-k layer while the second layer provides low resistance, resolving the contradiction between reliability and gate resistance.
Solution Approach 2:
The patent changes the deposition temperature parameter from a single high temperature to a two-stage process with low temperature (300-400°C) followed by high temperature (400-600°C). This parameter change enables the first layer to be deposited without etching the high-k layer, while the second layer provides the desired low resistance properties.
2Reliability
If low-temperature TiN layer is deposited first, then high-k loss is reduced and NBTI is mitigated, but additional processing steps are required
Solution Approach 1:
The patent combines multiple functions into the two-layer structure: the first TiN layer simultaneously serves as a protective layer during deposition and as part of the final work function gate stack. The second TiN layer is then deposited on top, merging the protection function with the low-resistance function in a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-layer TiN stack effectively reduces high-k loss, enhances NBTI, and maintains device performance by incorporating chlorine into the high-k layer, improving reliability and reducing gate resistance.
Implementation Method 1
a low-temperature first TiN layer rich in chlorine and a high-temperature second TiN layer, where the first TiN layer is incorporated into the high-k layer to mitigate NBTI and maintain high-k thickness
Implementation Method 2
depositing a first titanium nitride (TiN) layer on the interfacial layer; depositing a second TiN layer on the first TiN layer
Data Source
AI summary
A method of making a semiconductor device includes growing an interfacial layer on a substrate; depositing a first titanium nitride (TiN) layer on the interfacial layer; depositing a second TiN layer on the first TiN layer, the first TiN layer and the second TiN layer forming a bilayer work function gate stack of a first transistor; depositing a work function gate stack of a second transistor on the interfacial layer adjacent to the bilayer work function gate stack and on the bilayer work function stack; and depositing a gate electrode material on the work function gate stack of the second transistor.