Dual Triggered MOS Transistor for Low Voltage ESD Protection
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection devices in semiconductor devices have high trigger voltages due to the avalanche breakdown voltage of GGNMOS transistors, and the area of RC circuits in GCNMOS and STNMOS transistors is increased to achieve lower trigger voltages, leading to inefficiencies.
Innovation Solution
A dual triggered transistor configuration that couples an RC circuit to the gate and substrate of MOS transistors, reducing the trigger voltage and area of the RC circuit by using NMOS or PMOS transistors with specific pad connections and inverter placements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a GGNMOS transistor is used for ESD protection, then the device structure is simple, but the trigger voltage is very high (over 6 to 7V)
Solution Approach 1:
The invention segments the triggering mechanism into two independent paths: one through the gate (using capacitor-coupled AC component detection) and another through the substrate (using RC-coupled AC component detection). This segmentation allows the transistor to trigger at lower voltages by utilizing alternative triggering paths rather than relying solely on high-voltage avalanche breakdown of the gate-drain junction.
Solution Approach 2:
The invention introduces intermediary components (capacitor C1 coupled to the gate and RC circuit coupled to the substrate) that mediate the triggering process. These intermediaries detect the AC component of the ESD pulse and transfer it to appropriate nodes (gate and substrate) to initiate transistor conduction at lower voltages, avoiding the need for direct high-voltage avalanche breakdown.
2Object-affected harmful factors
If a GCNMOS or STNMOS transistor is used to lower trigger voltage, then the trigger voltage is reduced, but the RC circuit area is increased
Solution Approach 1:
The invention merges the gate-triggering path (via capacitor C1) and substrate-triggering path (via RC circuit) into a single dual-triggered transistor structure. This combination allows the system to utilize both triggering mechanisms simultaneously, achieving lower trigger voltage while optimizing the RC circuit dimensions since only one RC circuit is needed rather than separate RC circuits for each triggering method.
Solution Approach 2:
The invention changes the operational parameters by utilizing the AC component of the ESD pulse (rather than relying solely on voltage magnitude) to trigger the transistor through the capacitor-coupled gate path. This parameter change enables triggering at lower voltages while allowing the RC circuit to be minimized in size since it only needs to provide substrate coupling rather than full triggering functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual triggered MOS (DTMOS) transistor configuration lowers the trigger voltage to half that of GGNMOS transistors while reducing the RC circuit area, achieving the same trigger voltage with smaller RC values compared to GCNMOS and STNMOS transistors, as demonstrated by simulation results.
Implementation Method 1
a capacitor in which one end thereof is connected to the first pad and the other end thereof is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor
Implementation Method 2
The base current triggers the operation of the NPN bipolar transistor 130 at a voltage lower than the gate ground avalanche breakdown voltage thereby lowering the trigger voltage as compared to the GGNMOS transistor
Implementation Method 3
If the voltage exceeds the avalanche breakdown voltage of the PN junction formed with a P-well region 105 as a base and the N-type impurity region 106 as a collector, a plurality of electron-hole pairs is produced in a depletion region of the PN junction region
Implementation Method 4
an electrostatic discharge protection device having a dual triggered transistor coupling an RC circuit to a gate of a transistor and a substrate to lower an trigger voltage
Data Source
AI summary
Disclosed is an electrostatic discharge protection device that has a low trigger voltage and protects an internal circuit from electrostatic discharge. The ESD protection device includes an NMOS transistor in which a first pad and a drain are connected to each other and a second pad and a source are connected to each other. A capacitor in which an end is connected to the first pad and the other end is connected to a gate of the NMOS transistor and a substrate contact of the NMOS transistor. The ESD protection devices also includes a resistor in which an end is connected to the second pad and the other end is connected to the capacitor. The first pad may be a power pad and the second pad may be a ground pad. Alternately, the first pad may be an input/output pad and the second pad may be a ground pad.