Dual-Voltage Data Buffer Without Large Level Shifters
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Solution Overview
Problem
Existing data buffers face performance and size limitations when operating across different voltage domains, as level shifters become large and slow when voltage differences exceed 200-300 mV, and reducing output ports shifts processing burden to slower voltage domains.
Innovation Solution
A data buffer design that dynamically adjusts its operating voltage between input and output operations, using control circuitry to maintain the lower voltage during input and higher voltage during output, thereby avoiding the need for slow level shifters and allowing the buffer to act as a self-contained unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If level shifters are used to convert voltage levels for data transfer between voltage domains, then voltage domain compatibility is achieved, but the level shifters become large and slow when voltage difference exceeds 200-300 mV
Solution Approach 1:
The data buffer dynamically changes its operating voltage based on the operation mode. During input operations, it operates at the first voltage to match the source domain. During output operations, it switches to the second voltage to match the sink domain. This dynamic voltage switching eliminates the need for static level shifters and enables fast data transfer while maintaining voltage domain compatibility.
Solution Approach 2:
The operating voltage parameter of the data buffer is changed according to the operation phase. The control circuitry switches the voltage supply to the data buffer between a first voltage (during input) and a second voltage (during output), allowing the buffer to adapt to different voltage domains without requiring slow level shifting circuitry.
2Area of stationary object
If fewer output ports are used to reduce level shifter requirements, then device size is reduced, but more processing work is done in the lower voltage domain which is inherently slower
Solution Approach 1:
The data buffer dynamically switches its operating voltage based on operation mode, allowing it to operate at higher voltage during output operations. This enables faster processing in the higher voltage domain while maintaining full output port functionality, thus improving productivity without increasing device size.
Solution Approach 2:
The data buffer operation is segmented into distinct input and output phases, each operating at appropriate voltage levels. This segmentation allows the buffer to perform data acquisition at lower voltage and data output at higher voltage, optimizing processing speed for each phase without requiring reduction in output ports.
3Device complexity
If the data buffer operates at a single fixed voltage, then circuit design is simplified, but it cannot efficiently interface with both voltage domains
Solution Approach 1:
The data buffer employs dynamic voltage switching controlled by control circuitry that monitors operation mode. The control circuitry switches the buffer's supply voltage between first and second voltages based on whether input or output operations are active, enabling efficient interfacing with both voltage domains while maintaining relatively simple circuit architecture.
Solution Approach 2:
The data buffer is designed to perform multiple functions by operating at different voltage levels. The same buffer circuitry can interface with both the first voltage domain (during input) and the second voltage domain (during output), making it a universal interface solution that handles both voltage domains without requiring separate dedicated circuits for each domain.
Data Source
AI summary
A data buffer comprises data storage circuitry; input circuitry to input data to be stored by the data storage circuitry at a first operating voltage; output circuitry to output stored data from the data storage circuitry at a second operating voltage different to the first operating voltage; and control circuitry to control an operating voltage of the data storage circuitry to be substantially the first operating voltage during a data input operation by the input circuitry and to be substantially the second operating voltage during a data output operation by the output circuitry.