Semiconductor dies including low and high workfunction semiconductor devices
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Solution Overview
Problem
Current semiconductor die manufacturing processes separate high speed computing devices and long term storage devices, leading to propagation delay and reduced data fidelity during data transfer between computing and storage memory devices.
Innovation Solution
A semiconductor die is formed with a first set of semiconductor devices having a low workfunction for high speed computing and a second set of semiconductor devices having a high workfunction for long term storage, both sets being integrated monolithically to reduce propagation losses and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high speed computing devices and long term storage devices are separated into different semiconductor dies, then each device can be optimized for its specific function, but propagation delay and data fidelity degradation occur during data transfer between the devices
Solution Approach 1:
The patent combines high speed computing devices and long term storage devices into a single semiconductor die, eliminating the need for data transfer between separate dies. This integration removes propagation delays and preserves data fidelity by keeping computing and storage functions within the same physical substrate, directly resolving the contradiction between separation-based optimization and transfer-based degradation.
Data Source
AI summary
A method of making a semiconductor die includes forming, over a substrate, a stack including insulating layers and sacrificial layers alternatively on top of each other; replacing a portion of first sacrificial layers located in a first portion of the stack to form first gate layers; forming first channel layers extending in a first direction in the first portion; forming first memory layers extending in the first direction in the first portion; replacing a portion of second sacrificial layers located in a second portion of the stack to form second gate layers; forming second channel layers extending in the first direction in the second portion; and forming second memory layers extending in the first direction in the second portion.