Dummy Block Warpage Control in Semiconductor Packaging
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Solution Overview
Problem
The challenge in wafer level packaging (WLP) technology is maintaining uniformity and controlling warpage in semiconductor structures, which is critical for preventing malfunctions in integrated circuits, especially as wafer size increases and manufacturing complexity grows.
Innovation Solution
The method involves placing dummy blocks on a carrier with a coefficient of thermal expansion between that of the carrier and the dies, and determining specific uncovered areas to adjust warpage, using techniques like flip placement, stencil placement, and pre-formation to ensure proper alignment and coverage, thereby controlling warpage within a predetermined range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the wafer size is increased to extend the number of chips per wafer, then productivity is improved, but manufacturing precision deteriorates due to warpage control difficulties
Solution Approach 1:
The patent applies local quality by placing dummy blocks at specific locations on the carrier rather than uniformly distributing materials. The dummy blocks are positioned in uncovered areas where dies are not present, creating localized compensation zones that address warpage in specific regions of the large wafer structure.
Solution Approach 2:
The patent changes the physical parameters of the carrier system by introducing dummy blocks with specific coefficients of thermal expansion. These dummy blocks alter the thermal and mechanical parameters of the carrier, enabling warpage control through parameter adjustment rather than changing the overall wafer size constraints.
2Adaptability or versatility
If multiple layers of different materials are stacked to increase functionality, then adaptability is improved, but manufacturing precision deteriorates due to offset issues
Solution Approach 1:
The dummy blocks are placed in specific uncovered areas where dies are not located, creating localized compensation zones. This local quality approach allows different regions of the multi-layer structure to have different material compositions, enabling precise control over thermal expansion and warpage in each layer while maintaining overall functionality.
3Manufacturing precision
If the carrier coverage ratio is increased to improve uniformity, then manufacturing precision is improved, but device complexity increases due to additional dummy blocks
Solution Approach 1:
The patent applies partial action by placing dummy blocks only in uncovered areas where dies are not present, rather than covering the entire carrier surface. This partial coverage approach achieves sufficient uniformity and warpage control without the excessive complexity of complete surface coverage, optimizing the balance between precision and simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively adjusts and controls warpage, improving process control and yield in semiconductor manufacturing by ensuring a desired curvature and uniformity, facilitating more efficient patterning and metallization processes.
Implementation Method 1
The plurality of dummy blocks has a coefficient of thermal expansion between a coefficient of thermal expansion of the carrier and a coefficient of thermal expansion of the plurality of dies
Data Source
AI summary
A method of manufacturing a semiconductor structure includes several operations. The several operations include placing a plurality of dies on a carrier; defining a first zone and a second zone in a top surface of the carrier; calculating a first coverage ratio in the first zone; calculating a second coverage ratio in the second zone; disposing a dummy block on a specified location of the top surface of the carrier if the difference between the first coverage ratio and the second coverage ratio is greater than a predetermined value; forming a molding compound on the carrier.