Dummy Capacitor Line Width Control for Etching Uniformity
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Solution Overview
Problem
Dummy capacitors in semiconductor devices often cause pattern defects, degrading yield and reliability due to their design and placement in the peripheral circuit region.
Innovation Solution
A semiconductor device design where dummy capacitors are formed with a larger area than ferroelectric capacitors but with a line width not exceeding the width of the ferroelectric capacitors, and are patterned to match the etching profiles, reducing the likelihood of pattern defects and residue formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy capacitors are formed with larger area to increase apparent occupancy and improve etching uniformity, then in-plane uniformity of etching is improved, but pattern defects occur more frequently
Solution Approach 1:
The patent applies local quality by giving dummy capacitors different planar area from ferroelectric capacitors while maintaining the same line width. This local differentiation in area allows dummy capacitors to occupy more space for etching uniformity without creating pattern defects, as the line width (critical for patterning) remains consistent while the area (affecting occupancy) is optimized locally for each capacitor type.
2Area of stationary object
If dummy capacitors are arranged in peripheral circuit region to increase apparent occupancy, then apparent occupancy of ferroelectric capacitors is increased, but yield and reliability are degraded due to pattern defects
Solution Approach 1:
The patent uses local quality by positioning dummy capacitors with larger planar area specifically in the peripheral circuit region to increase apparent occupancy, while maintaining standard line width to avoid pattern defects. This localized area differentiation allows occupancy optimization without compromising yield.
3Area of stationary object
If dummy capacitors have different area from ferroelectric capacitors, then apparent occupancy is increased, but etching profile uniformity may be compromised
Solution Approach 1:
The patent resolves this contradiction by applying local quality differently: dummy capacitors have larger planar area for occupancy but maintain the same line width as ferroelectric capacitors. This selective local differentiation ensures that the critical dimension for etching (line width) remains uniform across all capacitors, while the area variation achieves the occupancy goal without compromising etching profile uniformity.
Data Source
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AI summary
A semiconductor device includes: a semiconductor substrate having a memory cell array region and a peripheral circuit region; a ferroelectric capacitor formed over the semiconductor substrate in the memory cell array region; and a dummy capacitor formed over the semiconductor substrate in the peripheral circuit region, with a layered structure same as that of the ferroelectric capacitor, with an area larger than that of the ferroelectric capacitor, and with a line width not larger than the width of the ferroelectric capacitor.