Dummy Cell Layout Optimization for Memory Yield
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Solution Overview
Problem
In semiconductor device fabrication, dummy cells used to maintain uniformity and process stability can contribute to yield loss if they are shorted to active circuitry or other features, and existing methods do not effectively optimize their layout to minimize failures.
Innovation Solution
The layout configuration of dummy cells can be modified to reduce failures by optimizing their size, shape, and position relative to active memory cells, using lithographic simulation and yield models to maximize yield and process window, and applying different design rules to dummy and active cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy cells are placed around the active array area to maintain uniformity and process stability, then manufacturing precision is improved, but reliability deteriorates due to potential shorts to active circuitry
Solution Approach 1:
The patent applies different design rules specifically to dummy cells compared to active cells. Dummy cells use relaxed design rules that allow larger spacing and different dimensional constraints, while active cells maintain strict design rules for functionality. This local differentiation resolves the contradiction by optimizing dummy cell layout for process stability without compromising active cell reliability.
Solution Approach 2:
The patent changes key layout parameters for dummy cells including increasing spacing between dummy cells and active circuitry, modifying dummy cell dimensions, and adjusting the number of dummy cells in peripheral regions. These parameter changes reduce the probability of shorts while maintaining the uniformity benefit, thus improving yield without sacrificing process stability.
2Manufacturing precision
If dummy cells are made with the same size and periodicity as regular memory cells to preserve regularity, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces different layout configurations for dummy cells versus active cells. While active cells maintain uniform size and periodicity, dummy cells in peripheral regions use different dimensions and spacing patterns. This local differentiation maintains printing regularity for active cells while simplifying the overall layout by allowing dummy cells to be optimized separately.
Solution Approach 2:
The patent segments the memory array layout into active region and dummy region, allowing independent optimization of each. The active region maintains strict periodicity for printing regularity, while the dummy region uses relaxed constraints. This segmentation reduces layout complexity by treating dummy cells as a separate design domain with its own rules.
3Productivity
If dummy cells are placed close to active cells to maximize array density, then productivity is improved, but reliability deteriorates due to increased failure probability
Solution Approach 1:
The patent optimizes the spacing parameter between dummy cells and active cells by applying relaxed design rules to dummy cells. This allows finding an optimal spacing value that maximizes array density while maintaining reliability by reducing the probability of shorts. The parameter optimization balances the competing requirements of density and failure reduction.
Solution Approach 2:
The patent uses dummy cells as copies of active cell structures but with modified parameters. These copied structures maintain the beneficial effect of uniformity while being optimized separately for reliability and density. The copying approach allows replication of the uniformity benefit without inheriting the full complexity and risk of active cell designs.
Data Source
AI summary
A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.