Dummy Cells Enhance Avalanche Capability in Power Semiconductor Devices
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Solution Overview
Problem
Semiconductor power devices exhibit weakened avalanche capability due to parasitic bipolar activation near the edge of the active area during unclamped inductive switching tests, leading to low and distributed UIS current measurements.
Innovation Solution
Incorporation of dummy cells along the edge of the active area without N+ source or emitter regions, which act as buffer cells to absorb avalanche energy, thereby preventing parasitic bipolar activation and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cells are positioned near the edge of active area to maximize active area utilization, then device area efficiency is improved, but parasitic bipolar turns on first causing weakened avalanche capability
Solution Approach 1:
The patent segments the edge cells into two categories: regular cells with N+ source regions and dummy cells without N+ source regions. This segmentation allows the dummy cells to serve a different function (absorbing avalanche energy) while regular cells perform normal switching operations, thus resolving the contradiction between area utilization and avalanche capability.
Solution Approach 2:
Dummy cells act as intermediary elements between the gate metal pad/gate runner and the regular cells. These dummy cells absorb avalanche energy and prevent parasitic bipolar activation in nearby regular cells, serving as a protective buffer that resolves the conflict between edge cell placement and avalanche performance.
2Power
If gate bias is increased to turn on channel, then device conductivity is improved, but parasitic bipolar turns on first near active edge reducing UIS current
Solution Approach 1:
The dummy cells are designed to preemptively absorb avalanche energy and prevent parasitic bipolar activation before it can affect regular cells during UIS events. This preliminary protective action occurs during avalanche conditions while maintaining normal channel conductivity during switching operations.
Solution Approach 2:
The patent converts the harmful effect of edge-proximity cells (which first turn on and cause parasitic bipolar activation) into a beneficial protective mechanism by creating dummy cells that intentionally absorb avalanche energy, thereby protecting regular cells and improving overall UIS current.
3Reliability
If dummy cells without N+ source region are added along edge of active area, then avalanche capability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by making only the edge cells (dummy cells) different from regular cells - specifically, dummy cells lack N+ source regions while regular cells have them. This localized structural difference is confined to edge positions, minimizing overall device complexity while achieving the avalanche protection function.
Solution Approach 2:
Instead of modifying all cells in the device, the patent applies the dummy cell concept only to edge cells that are most susceptible to parasitic bipolar activation. This partial action approach achieves avalanche protection with minimal increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of dummy cells increases UIS current values and narrows their distribution, reducing the likelihood of failure sites near the edge of the active area and improving the overall avalanche capability of semiconductor devices.
Implementation Method 1
dummy cells composed of at least one cell along edge of active area without N+ source (or emitter region for trench IGBT) region are employed according to the present invention... Said dummy cells having no parasitic bipolar act as buffer cells to absorb avalanche energy at UIS test when gate bias is started to be increased
Data Source
AI summary
A structure of power semiconductor device having dummy cells around edge of active area is disclosed. The UIS test result of said improved structure shows that failed site after UIS test randomly located in active area which means avalanche capability of the semiconductor power device is enhanced by implementation of the dummy cells.


