Dummy Column Memory Layout for IMC Side-Channel Protection

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Solution Overview

Problem

In-memory computation (IMC) processing systems are vulnerable to side channel attacks that attempt to extract proprietary computational weight data, necessitating improved security measures.

Innovation Solution

The implementation of dummy columns in the memory array, coupled with bitline precharge circuits that randomly vary voltage levels during operations, introduces randomness in power consumption patterns, making it difficult for attackers to decipher the stored data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy columns are added to the memory array, then security against side channel attacks is improved, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory array is segmented into functional columns and dummy columns. The dummy columns are separate segments that do not store actual computational weight data but instead generate random power consumption patterns. This segmentation allows the system to maintain security without compromising the integrity of the actual data storage columns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Dummy columns act as intermediaries between the actual data storage and the power consumption measurement. These intermediary columns introduce random power consumption that masks the power signatures of actual data operations, thereby protecting the computational weight data from side channel attacks without requiring changes to the core data storage mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If bitline precharge circuits are used to randomize voltage levels, then security against power-based attacks is improved, but device complexity increases

Engineering Contradiction:
ImprovesecurityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bitline precharge circuits dynamically randomize voltage levels during operation. Instead of using fixed voltage levels, the system randomly selects between different voltage levels (e.g., Vdd and ground) for precharging dummy column bitlines. This dynamic randomization creates variable power consumption patterns that effectively mask the power signatures of actual data operations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the voltage level parameter of the bitlines during operation. By randomly selecting between different voltage levels for precharging dummy columns, the system creates parameter variation in power consumption that obscures the relationship between power measurements and actual data values, thereby defeating power-based side channel attacks.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If dummy columns are implemented in the memory array, then power consumption patterns are obscured, but manufacturing complexity increases

Engineering Contradiction:
Improvepower consumption patternsVSAvoidmanufacturing complexity
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The dummy columns are designed with the same structural characteristics as the functional columns, using identical memory cell arrangements, word line connections, and bit line structures. This homogeneity allows the dummy columns to be manufactured using the same processes as the functional columns, minimizing additional manufacturing complexity while still achieving the security objective of obscuring power consumption patterns.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentUS20250372158A1Scrambled dummy column memory architecture for an in-memory computation processing system
Publication Date: 2025.12.04 STMICROELECTRONICS INT NV
  • US20250372158A1 patent drawing
  • US20250372158A1 patent drawing
  • US20250372158A1 patent drawing

AI summary

A circuit memory includes sub-arrays with memory cells (storing weight data for an in-memory computation operation) arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. For in-memory computation operation execution, a control circuit simultaneously actuates one word line per sub-array. An input/output circuit for each column includes bit line inputs to the local bit lines of the sub-arrays and a sub-array data output coupled to each bit line input. Bit lines of the sub-arrays in a dummy column of the memory are precharged to a randomly selected one of first and second voltage levels in connection with execution of the in-memory computation operation to provide a randomization of circuit power consumption as a measure to protect the memory from a side channel attack to extract the weight data.