Dummy Fill Region for Passive Device Topography Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of passive devices, such as metal-based resistors, over non-planar surfaces in semiconductor fabrication can lead to performance issues due to localized over-polishing and high capacitive coupling with the substrate, which conventional dummy fill methods fail to adequately address.
Innovation Solution
A structure and method involving shallow trench isolation regions, semiconductor fins, and a moat region with lightly-doped semiconductor material, along with specific gate and contact arrangements, are used to create a dummy fill region that reduces capacitive coupling and improves topography control, allowing for the formation of a passive device with enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dummy fill with field-effect transistor features is used, then topography control during chemical mechanical polishing is improved, but capacitive coupling between the passive device and substrate increases
Solution Approach 1:
The dummy fill structure is segmented into multiple functional components: shallow trench isolation regions provide mechanical support and define boundaries, semiconductor fins provide topography control, while gate structures and source/drain regions are configured to minimize capacitive coupling. This segmentation allows each component to fulfill its specific function without the harmful capacitive effects of conventional continuous dummy fill.
Solution Approach 2:
Different regions of the dummy fill structure have different properties optimized for their specific functions. The shallow trench isolation regions provide electrical isolation, the semiconductor fins provide topography control, and the gate structures are positioned to minimize capacitive coupling. This local optimization resolves the contradiction between maintaining topography and reducing capacitive coupling.
2Ease of manufacture
If passive devices are formed over non-planar surfaces, then manufacturing process is simplified, but performance of the passive device deteriorates due to localized over-polishing
Solution Approach 1:
The shallow trench isolation regions and semiconductor fins are formed beforehand to create a planarized surface structure before the passive device formation. This preliminary topography control prevents localized over-polishing during subsequent chemical mechanical polishing steps, ensuring uniform passive device performance while maintaining manufacturing simplicity.
3Manufacturing precision
If dummy fill is used to control topography, then polishing uniformity is improved, but heat dissipation from passive devices is reduced
Solution Approach 1:
The shallow trench isolation regions act as intermediary structures that provide both topography control for uniform polishing and thermal pathways for heat dissipation. The semiconductor fins similarly serve as intermediaries that maintain surface planarity while conducting heat away from the passive device region, thus resolving the contradiction between polishing uniformity and heat dissipation.
Data Source
AI summary
Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.