Intelligent Dummy Fill Placement for Inter-Layer Capacitance Reduction
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Solution Overview
Problem
Existing dummy fill methodologies in integrated circuit fabrication result in large overlaps between successive layers, leading to increased unwanted bulk capacitance and signal delays, as they treat each layer independently and do not effectively address adverse effects on electric fields.
Innovation Solution
An intelligent dummy fill placement method that treats each consecutive pair of layers together, using alternating dummy fill features to form checkerboard patterns and avoid overlaps, thereby minimizing inter-layer capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If conventional dummy fill methodologies are used to even topography and pattern density across the chip, then CMP planer profile variation is reduced, but large overlaps between successive layers occur leading to increased unwanted bulk capacitance
Solution Approach 1:
The patent combines the dummy fill placement for multiple successive layers into a unified optimization process. Instead of treating each layer independently, the system simultaneously considers dummy fill placements across multiple layers to minimize inter-layer capacitance while maintaining CMP uniformity, thereby merging what were previously separate optimization problems into a coordinated approach.
Solution Approach 2:
The patent applies local quality by allowing different dummy fill strategies in different regions of the chip. The system identifies specific areas where overlaps occur and applies targeted dummy fill placements to reduce capacitance in those local regions, rather than applying a uniform approach across the entire chip. This enables localized optimization of capacitance reduction while maintaining overall CMP uniformity.
2Manufacturing precision
If dummy fills are added to unused areas to satisfy minimum metal coverage requirements, then pattern density uniformity is improved, but overlap areas between successive layers increase leading to signal delays
Solution Approach 1:
The patent transitions from two-dimensional dummy fill placement (within a single layer) to three-dimensional placement optimization across multiple layers. By considering the vertical dimension and inter-layer relationships, the system can place dummy fills in positions that satisfy in-layer density requirements while minimizing overlaps with adjacent layers, thereby reducing capacitance and signal delay without sacrificing pattern density uniformity.
Solution Approach 2:
The patent changes the optimization parameters from single-layer density metrics to multi-layer capacitance metrics. The system modifies the objective function to include inter-layer overlap minimization alongside pattern density uniformity, allowing the dummy fill placement to be optimized for multiple competing parameters simultaneously. This enables the system to find placements that balance density requirements with capacitance reduction.
3Ease of manufacture
If each layer is treated independently for dummy fill placement, then manufacturing simplicity is maintained, but large overlaps occur between successive layers increasing inter-layer capacitance
Solution Approach 1:
The patent applies segmentation by dividing the multi-layer optimization problem into manageable segments. The system processes successive pairs of layers in a systematic sequence, optimizing dummy fill placements for each pair while building upon previous placements. This segmented approach maintains computational tractability and manufacturing feasibility while still achieving the benefit of reduced inter-layer capacitance through coordinated multi-layer optimization.
Data Source
AI summary
The present invention is directed to a method and system of intelligent dummy filling placement to reduce inter-layer capacitance caused by overlaps of dummy filling area on successive layers. The method and system treats each consecutive pair of layers together so as to minimize dummy filling overlaps between each layer. In particular, dummy fill features on each layer may be placed in a checkerboard pattern to avoid overlaps. As such, the present invention may eliminate large overlap area of the dummy patterns on consecutive layers by utilizing intelligent dummy filling placement.