Dummy Fin Cell Placement for CMP Loading Uniformity
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Solution Overview
Problem
In integrated circuit (IC) design, the increasing demand for higher drive currents in smaller transistors poses challenges in maintaining uniform polysilicon gate density and preventing chemical mechanical polishing (CMP) loading, which can affect device performance and functionality.
Innovation Solution
The placement of dummy fin cells in IC layouts, which are derived from standard dummy fin cells and expanded to minimize unfilled regions and enhance polysilicon gate density, helps in maintaining even polysilicon gate distribution and reducing CMP loading by facilitating more uniform photolithography operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy fin cells are placed in empty regions to maintain uniform polysilicon gate density, then CMP loading is reduced and device performance is improved, but the device complexity and layout design complexity increase
Solution Approach 1:
The patent applies local quality by differentiating between core region dummy fin cells and I/O region dummy fin cells. Core region dummy fin cells have a first configuration while I/O region dummy fin cells have a second configuration, allowing each region to receive appropriate dummy structures tailored to its specific CMP loading requirements without unnecessarily complicating the entire layout.
Solution Approach 2:
The patent segments the dummy fin cell placement into distinct regions (core region and I/O region) with different configurations. This segmentation allows the layout to address CMP loading issues in each region independently, reducing overall complexity by treating different areas differently rather than applying a uniform approach across the entire chip.
2Quantity of substance
If dummy fin cells are expanded to minimize unfilled regions, then polysilicon gate density is enhanced and device performance is improved, but the layout design complexity and file size increase
Solution Approach 1:
The patent changes parameters by varying the dimensions and configurations of dummy fin cells based on their location. Core region dummy fin cells have different parameters (first configuration) compared to I/O region dummy fin cells (second configuration), optimizing polysilicon gate density through parameter adjustment rather than uniform expansion, thereby managing complexity.
3Stability of the object's composition
If dummy fin cells are placed closer to active fins to reduce empty space, then polysilicon gate distribution uniformity is improved, but the risk of affecting active fin functionality increases
Solution Approach 1:
The patent applies local quality by creating different dummy fin cell configurations for different regions. Core region dummy fin cells are positioned and sized differently from I/O region dummy fin cells, allowing each region to achieve uniform polysilicon gate distribution without compromising active fin functionality through inappropriate proximity or configuration.
Data Source
AI summary
In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.