Dummy Fin Contact for Bottom Access in Stacked Transistors
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Solution Overview
Problem
The challenge in forming stacked transistors is that when only one transistor is needed, the process of forming multiple transistors simultaneously makes it difficult to isolate and access a single bottom transistor without forming an unnecessary top transistor, leading to inefficiencies and increased complexity.
Innovation Solution
The use of a dummy fin structure allows for the formation of a self-aligned contact to the bottom transistor, replacing the unnecessary top transistor and enabling access while maintaining the benefits of stacked transistor configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple transistors are formed simultaneously in a stacked configuration, then space utilization is improved, but the complexity of forming high aspect-ratio structures increases and manufacturing difficulty worsens
Solution Approach 1:
The patent divides the transistor formation process into separate stages: first forming the bottom transistor, then forming the top transistor. This segmentation allows each transistor to be formed independently with optimized process parameters, reducing the overall complexity while maintaining space utilization benefits of stacked configuration
Solution Approach 2:
The bottom transistor is formed first as a preliminary structure before forming the top transistor. This preliminary action establishes a foundation that simplifies subsequent top transistor formation, as the bottom transistor structure is already in place to support the stacked configuration without requiring simultaneous high aspect-ratio formation
2Ease of operation
If a top transistor is formed in a stacked configuration, then access to the bottom transistor is blocked, but forming only a single transistor wastes the stacked structure capability
Solution Approach 1:
The patent extracts the top transistor from the stacked configuration when it is not needed for the circuit design. By removing the unnecessary top transistor, direct access to the bottom transistor is achieved while still utilizing the stacked structure capability when needed, optimizing both ease of operation and productivity
Solution Approach 2:
The patent applies different structural configurations to different regions of the chip: stacked transistors where both top and bottom are needed, and single transistors with direct access where only the bottom transistor is required. This local quality approach optimizes each region according to its specific functional requirements
Data Source
AI summary
A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.