Dummy Gate Sequencing for Void-Free Channel-Last FinFETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device fabrication, the formation of dummy gates often results in voids or seams between real channels, which can lead to device yield reduction and processing challenges, especially in FinFET and GAAFET production.
Innovation Solution
The method involves depositing a first dummy gate material over semiconductor fins before forming dummy fins, followed by a second dummy gate material deposition, thereby avoiding voids or seams during the dummy gate formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates are formed using conventional methods, then device density is maintained, but voids or seams appear between real channels leading to yield reduction
Solution Approach 1:
The method performs preliminary actions by forming a first dummy gate material before forming the dummy fins, and then forming a second dummy gate material over the first dummy gate material. This preliminary sequencing of operations ensures that the dummy gate structure is established in a controlled manner that prevents void formation, thereby improving both manufacturing precision and device yield.
Solution Approach 2:
The dummy gate formation process is segmented into multiple distinct steps: forming a first dummy gate material, forming dummy fins, and forming a second dummy gate material. This segmentation allows each step to be optimized independently, ensuring complete coverage and eliminating the formation of voids or seams that would occur in a single-step process.
2Reliability
If advanced non-planar transistor architectures are used, then device performance increases, but processing complexity increases
Solution Approach 1:
The preliminary formation of the first dummy gate material establishes a foundation that simplifies subsequent processing steps. By preparing this initial structure before forming the dummy fins and second dummy gate material, the method reduces the complexity of handling advanced non-planar architectures while maintaining their performance benefits.
Solution Approach 2:
The first dummy gate material acts as an intermediary structure that facilitates the formation of the final dummy gate. This intermediate layer simplifies the processing of complex non-planar transistor architectures by providing a stable base for subsequent deposition and patterning steps, thereby reducing overall processing complexity.
3Manufacturing precision
If multiple deposition steps are used for dummy gate formation, then seamless formation is achieved, but processing time increases
Solution Approach 1:
The deposition process is segmented into two targeted steps: forming the first dummy gate material and forming the second dummy gate material. This segmentation achieves seamless dummy gate formation by ensuring complete coverage in each step, while the efficiency of each individual deposition step minimizes the overall time penalty compared to a single prolonged deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device yield by ensuring seamless dummy gate formation, enhancing the processing efficiency and performance of non-planar transistors like FinFETs and GAAFETs.
Implementation Method 1
depositing a first dummy gate material over semiconductor fins
Implementation Method 2
followed by a second dummy gate material deposition
Data Source
AI summary
A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.