Dummy Metal Filling Method Reducing Parasitic Capacitance
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Solution Overview
Problem
In integrated circuit processes, the micro-loading effect leads to nonuniformity in etching or polishing rates due to different wafer densities, causing additional parasitic capacitance when dummy metal is filled, which decreases chip processing speed.
Innovation Solution
A dummy metal filling method that determines to-be-filled regions in metal pattern layers based on wiring connections and fills same-layer metal wires to increase potential line width, reducing the area of dummy metal needed and minimizing parasitic capacitance, while adding dummy metal to improve pattern density and flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy metal is filled to low-density regions to improve pattern uniformity, then pattern density and flatness are improved, but parasitic capacitance increases and chip processing speed decreases
Solution Approach 1:
The patent applies local quality by differentiating between functional metal wires and dummy metal based on their purposes. Same-layer metal wires are strategically placed in low-density regions to provide both density improvement and electrical functionality, while dummy metal is minimized or eliminated in critical signal paths. This selective approach ensures that pattern uniformity is improved without unnecessarily increasing parasitic capacitance in functional areas.
Solution Approach 2:
The patent makes metal wires multi-functional by having them serve both as electrical interconnects and as density-filling elements. By identifying same-layer and same-net metal wires that can be extended into low-density regions, the solution achieves dual purposes: maintaining electrical connectivity while improving pattern density and reducing micro-loading effects, thereby eliminating the need for separate dummy metal in many cases.
2Manufacturing precision
If dummy metal is added to improve pattern density, then etching and polishing uniformity are improved, but chip processing speed decreases due to increased parasitic capacitance
Solution Approach 1:
The patent changes the parameter of metal distribution by dynamically adjusting metal wire placement based on local pattern density. Same-layer metal wires are extended into low-density regions where needed to achieve uniform etching and polishing, while avoiding areas where parasitic capacitance would critically impact speed. This parameter-based approach allows optimization of both manufacturing precision and electrical performance.
3Stability of the object's composition
If more dummy metal is filled to improve flatness, then pattern density increases, but the area occupied by dummy metal increases and parasitic capacitance increases
Solution Approach 1:
The patent extracts the essential function of dummy metal (providing density and flatness) and separates it from its traditional implementation. Instead of adding dummy metal everywhere, the solution extracts only the necessary density-providing metal extensions (same-layer metal wires) in specific low-density regions, eliminating unnecessary dummy metal area while maintaining flatness through targeted metal placement.
Data Source
AI summary
Embodiments provide a dummy metal filling method and apparatus, a device and a medium, and relates to the field of semiconductor fabrication technologies. The method includes: providing an initial layout including a potential line; determining same-layer and same-net metal wires of each metal pattern layer based on a wiring connection relationship in the initial layout; determining a to-be-filled region in the each metal pattern layer based on the same-layer and same-net metal wires; filling same-layer metal wires into the to-be-filled region in the each metal pattern layer, and adding a connection hole, such that the same-layer metal wires are connected to the same potential line; and adding dummy metal on a layout where the filling the same-layer metal wires is completed, to output a target layout.