Dummy Pattern Layout for CMP Uniformity in Semiconductor Wafers
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Solution Overview
Problem
The CMP method used for planarizing interlayer insulating films in semiconductor manufacturing often results in over-polishing in areas with low wiring density, such as the scribed area, leading to thin films and reliability issues in semiconductor chip formation, due to interference from dummy patterns.
Innovation Solution
The method involves laying out first and second dummy patterns with specific distances from each other and the wiring layers in the semiconductor wafer, preventing over-polishing in the chip formation area while allowing polishing in the scribed area, thereby increasing wiring density adjacent to the scribed area without complex logical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP method is used to planarize interlayer insulating film, then flatness of upper surface is improved, but over-polishing occurs in low wiring density areas causing film thinning
Solution Approach 1:
The patent applies local quality by differentiating the treatment of different areas on the semiconductor wafer. Dummy patterns are selectively placed only in the chip formation area where wiring density is low, while the scribed area remains without dummy patterns. This creates locally different polishing characteristics - the chip area receives protection from over-polishing through dummy patterns, while the scribed area maintains its natural low-density state for proper CMP processing.
Solution Approach 2:
The patent segments the wafer surface into distinct functional zones: chip formation area and scribed area. By applying dummy patterns only to specific regions (chip area) and not others (scribed area), the solution divides the uniform wafer surface into non-uniform zones with different wiring density characteristics, allowing differentiated CMP processing outcomes for each zone.
2Reliability
If dummy patterns are laid out to increase wiring density, then over-polishing is prevented, but interference with marks and patterns occurs
Solution Approach 1:
The patent uses local quality by restricting dummy pattern placement to specific regions away from marks and critical patterns. Dummy patterns are positioned in areas where they provide polishing protection without creating interference zones. This spatial differentiation ensures that the protective function of dummy patterns is achieved while avoiding harmful interference with alignment marks and functional patterns.
Solution Approach 2:
The dummy patterns act as intermediary elements that mediate between the CMP polishing process and the underlying wiring structure. They provide a protective function during polishing while being spatially separated from marks and critical patterns, thus serving as a buffer that prevents over-polishing without causing interference with other wafer features.
3Manufacturing precision
If wiring density is increased in chip formation area, then CMP uniformity is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by placing dummy patterns only in specific regions of the chip formation area where wiring density is low and CMP uniformity needs improvement. The dummy patterns are strategically positioned to achieve polishing uniformity without creating excessive parasitic capacitance in functional wiring regions. This localized approach optimizes CMP uniformity while minimizing harmful electrical effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents interlayer insulating film thinning and potential short circuits by maintaining adequate film thickness and reducing parasitic capacitance, ensuring reliable semiconductor chip formation and preventing over-polishing in the semiconductor chip formation area.
Implementation Method 1
a CMP (Chemical Mechanical Polishing) method is generally used to planarize the upper surface of an interlayer insulating film
Data Source
AI summary
A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first area may be surrounded by a scribed area of the semiconductor wafer. The first area includes a second area bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to a boundary between the first area and the second area. A first dummy pattern in the first area is laid out to have at least a first distance from the first wiring. A second dummy pattern in the second area is laid out to have at least the first distance from the first wiring and at least a third distance from the first dummy pattern.