Graduated Dummy Pattern Layout Around TSVs to Reduce Warpage
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Solution Overview
Problem
Existing through-silicon via (TSV) formation processes lead to warpage issues in device dies and wafers, which are not adequately addressed by current methods.
Innovation Solution
The introduction of dummy patterns around TSVs with varying pattern densities, where regions closer to the TSV have lower densities and those farther away have higher densities, to mitigate warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV formation processes are used, then the manufacturing process is simple, but warpage issues occur in device dies and wafers
Solution Approach 1:
Dummy patterns are formed in advance around TSV locations before the TSV etching process. This preliminary action compensates for anticipated stress and warpage issues that would occur during and after TSV formation, preventing warpage problems before they manifest in the final product.
Solution Approach 2:
Dummy patterns are strategically placed only in specific regions around TSVs where warpage is most likely to occur, rather than uniformly across the entire wafer. The pattern density varies locally - higher density near TSVs and lower density farther away - to provide targeted stress compensation exactly where needed.
2Manufacturing precision
If dummy patterns with varying densities are introduced around TSVs, then warpage is reduced, but manufacturing complexity increases
Solution Approach 1:
The dummy pattern region around each TSV is divided into multiple zones with different pattern densities. The first dummy pattern region has a higher density of dummy patterns, while the second dummy pattern region has a lower density. This segmentation allows precise control of stress compensation at different distances from the TSV.
Solution Approach 2:
The pattern density parameter of dummy patterns is systematically varied based on distance from the TSV. By changing the density parameter - higher near the TSV, lower farther away - the solution optimizes stress compensation effectiveness while providing a clear, manufacturable pattern design rule.
Data Source
AI summary
A method includes forming an integrated circuit device on a semiconductor substrate, forming a through-via penetrating through the semiconductor substrate, and forming dummy patterns surrounding the through-via. The dummy patterns include a first plurality of dummy patterns having a first pattern density, and a second plurality of dummy patterns. The first plurality of dummy patterns are between the through-via and the second plurality of dummy patterns. The second plurality of dummy patterns have a second pattern density different from the first pattern density.


