Dummy Structures for CMP Dishing in Embedded Poly-SiON CMOS
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Solution Overview
Problem
The integration of logic devices and memory devices on a shared semiconductor chip using high-k metal gate transistors faces issues with metal residue accumulation in the boundary region, leading to high leakage current and electrical shorts, as well as material removal during chemical mechanical polishing (CMP) processes, which affects device performance and increases processing costs.
Innovation Solution
Incorporating one or more dummy structures on either side of the boundary region between the embedded memory and periphery regions to create a more even surface profile during deposition, preventing CMP dishing and reducing polysilicon loss, thereby mitigating electrical shorts and leakage issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k metal gate transistors are used to improve device performance, then device performance is improved, but metal residue accumulates in the boundary region causing high leakage current and electrical shorts
Solution Approach 1:
Dummy structures are formed in the boundary region before the main fabrication processes to preemptively prevent metal residue accumulation. These dummy structures serve as sacrificial elements that absorb or redirect metal deposition, preventing residue from accumulating in critical boundary areas where it would cause leakage or shorts.
Solution Approach 2:
The dummy structures act as intermediary elements between the embedded memory and periphery regions. They mediate the metal deposition process by providing alternative sites for metal accumulation, thereby protecting the boundary region from harmful metal residue buildup that would otherwise occur during high-k metal gate formation.
2Ease of manufacture
If conventional fabrication processes are used without dummy structures, then processing is simpler, but CMP dishing occurs and polysilicon is lost during material removal
Solution Approach 1:
Dummy structures are selectively placed only in the boundary region where surface profile uniformity is critical for CMP processing. This localized approach improves surface profile uniformity in the specific area needing it, while maintaining processing simplicity elsewhere in the device structure.
3Object-generated harmful factors
If additional boundary cut process is implemented to remove metal residue, then leakage is reduced, but processing complexity and costs increase
Solution Approach 1:
The dummy structures are formed in advance to prevent metal residue accumulation before it becomes a problem. This preliminary action eliminates the need for subsequent boundary cut processes, as the dummy structures have already mitigated the residue accumulation issue during the main fabrication sequence.
Solution Approach 2:
The dummy structures, which initially appear to be unnecessary additions, actually convert the potential harm of metal residue accumulation into a beneficial effect by providing controlled sites for metal deposition. This transforms what would be a harmful accumulation into a managed process feature, eliminating the need for additional corrective processing steps.
Data Source
AI summary
The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.