Dummy Vertical Structures for Uniform Etching in 3D NAND Memory
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Solution Overview
Problem
The manufacturing of three-dimensional integrated circuit memory devices is complicated by differences in etch rates between array and pad regions, requiring multiple cuts and increasing costs due to the need for different etch rates for conductive material layers.
Innovation Solution
A structure with isolation blocks inside the array region allows for a single cut using a single mask, utilizing a uniform etch rate for both memory cell and non-memory cell vertical pillars, simplifying the manufacturing process by maintaining a consistent etch rate across both types of pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple cuts with different etch rates are used to cut through the same number of layers in array and pad regions, then the etching precision is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent introduces dummy vertical structures in the pad region that have the same etch characteristics as the vertical pillars in the array region. This creates structural homogeneity between the two regions, allowing a single etch rate to be used for cutting through the same number of layers in both regions, thereby simplifying the manufacturing process while maintaining etching precision
Solution Approach 2:
The patent segments the pad region by introducing dummy vertical structures that are separated from the actual pad structures by isolation blocks. This segmentation allows the dummy structures to serve a specific function (matching etch rate) without interfering with the electrical function of the actual pads, resolving the contradiction between precision and complexity
2Manufacturing precision
If multiple cuts with different etch rates are used to accommodate different structures in array and pad regions, then the manufacturing precision is improved, but the loss of time and productivity decrease
Solution Approach 1:
By creating structural homogeneity through dummy vertical structures, the patent enables a single etching process to be used for both array and pad regions, eliminating the need for multiple sequential etching steps with different parameters, thereby improving manufacturing efficiency while maintaining precision
Solution Approach 2:
The dummy vertical structures are formed in advance during the same fabrication steps as the actual vertical pillars, before the etching process. This preliminary action ensures that the etch rate matching is already in place, allowing the subsequent etching step to proceed uniformly across both regions without requiring additional time for multiple etching passes
3Ease of manufacture
If isolation blocks are placed outside the array boundary, then the separation of conductive lines from pads is achieved, but the etch rate uniformity is compromised
Solution Approach 1:
The patent moves the isolation function from the horizontal plane (outside array boundary) to the vertical dimension by placing isolation blocks that extend vertically between the dummy vertical structures and the pad region. This dimensional transition allows the isolation blocks to separate conductive lines from pads while maintaining the horizontal continuity needed for uniform etching across the array boundary
Data Source
AI summary
A memory device comprises a stack of patterned conductor layers, at least a plurality of the layers comprising conductive strips including strips continuous with a pad and other strips isolated from the pad. An array of vertical pillars extends through the stack of patterned conductor layers, wherein memory cells are disposed at cross-points between the vertical pillars and patterned conductor layers. The array has an array boundary proximal to the pad. A first set of isolation blocks extends through the plurality of patterned conductor layers separating the strips continuous with the pad from the other strips isolated from the pad. A second set of isolation blocks inside the array boundary extends through the plurality of patterned conductor layers isolating the other strips from the pad.