Duplex Plated Bump-on-lead Pad Vertical Offset for Finer Pitch
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Solution Overview
Problem
Conventional semiconductor packages require a significant distance and pitch between conductive bumps and adjacent traces to avoid electrical shorts, which limits signal trace routing density and increases package size.
Innovation Solution
A method of forming duplex plated bump-on-lead (BOL) pads over a substrate, where a conductive layer is formed with BOL pads vertically offset from conductive traces, and an insulating layer is used to isolate the surface of the conductive traces, allowing for reduced clearance and pitch between adjacent bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages use standard bump mounting without vertical offset, then manufacturing process is simpler, but electrical shorts occur between bumps and adjacent traces
Solution Approach 1:
The patent introduces a vertical offset between the BOL pads and adjacent conductive traces by forming the BOL pads at a different elevation level. This dimensional separation in the vertical direction prevents electrical shorts while allowing closer horizontal spacing, thus improving reliability without significantly increasing overall device complexity.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the BOL pads and adjacent conductive traces. This intermediate insulating structure provides electrical isolation and prevents shorts, while the duplex plating structure provides enhanced electrical connection. Together these intermediaries resolve the contradiction between reliability and complexity.
2Reliability
If larger clearance is maintained between bumps and adjacent traces, then electrical shorts are avoided, but signal trace routing density decreases
Solution Approach 1:
By moving the BOL pads to a different vertical level through the vertical offset structure, the patent eliminates the need for large horizontal clearance between bumps and traces. This allows signal traces to be routed much closer to the bumps, significantly increasing routing density while maintaining electrical reliability through the vertical separation.
3Reliability
If larger pitch is used between adjacent bumps, then electrical shorts are prevented, but package size increases
Solution Approach 1:
The vertical offset structure separates BOL pads from adjacent traces in the vertical dimension, allowing adjacent bumps to be positioned much closer together in the horizontal plane without risk of electrical shorts. This enables smaller pitch between bumps and reduces overall package footprint while maintaining reliability.
4Productivity
If duplex plated BOL pads with vertical offset are formed, then finer pitch between traces is achieved, but manufacturing process complexity increases
Solution Approach 1:
The pad formation process is segmented into distinct stages: forming conductive traces at one level, forming BOL pads at a different vertical level with insulating material between them, and then selectively removing insulating material to expose BOL pad surfaces. This segmentation allows complex duplex plated structures to be manufactured through systematic step-by-step processes.
Solution Approach 2:
The patent employs preliminary actions by first forming the complete duplex plated BOL pad structure with vertical offset and insulating layers before final trace routing and bump mounting. This preliminary structuring simplifies subsequent manufacturing steps and enables finer pitch implementation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of electrical shorts and allows for a finer pitch between conductive traces, enhancing signal routing density and minimizing package size while maintaining reliable electrical connections.
Implementation Method 1
forming a conductive layer over the substrate to provide electrical interconnect laterally across the substrate
Implementation Method 2
forming an insulating layer over the substrate to completely cover and electrically isolate a surface of the second portion of the conductive layer
Data Source
AI summary
A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.