DUT Array Matrix for Precise Defect Localization
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Solution Overview
Problem
Current wafer acceptance testing methods are inefficient in locating and quantifying defects, as they require time-consuming visual inspections and occupy large areas on the wafer, making it difficult to determine the exact location of defects and requiring additional electron microscope examinations.
Innovation Solution
A DUT array with a matrix arrangement of test units, bit lines, and word lines, where each test unit has a first and second terminal, with the second terminals connected to ground, allowing for efficient defect detection by applying voltages to bit and word lines and reading output signals from sense amplifiers to systematically check for defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional test structures with input/output pads are used, then defects can be detected, but the test structures occupy large area on the wafer and defect location cannot be precisely determined
Solution Approach 1:
The test structures are segmented into multiple test units arranged in a matrix array, where each test unit has unique row and column identifiers. This segmentation allows precise defect localization by identifying which specific test unit exhibits the defect, reducing the area each test unit occupies while maintaining detection capability.
Solution Approach 2:
Each test unit in the matrix is assigned unique local identifiers (row and column signals) that provide local quality differentiation. This allows the system to identify the specific location of defects within the matrix array, transforming the inability to locate defects into a precise localization capability.
2Measurement precision
If visual inspection and electron microscope examinations are performed to locate defects, then defect analysis can be conducted, but the process is time-consuming and costly
Solution Approach 1:
The patent replaces the mechanical visual inspection process with an electrical measurement system. By applying test signals to specific row and column lines and measuring the response, the system electrically identifies defect locations without requiring time-consuming visual or microscopic examination by engineers.
Solution Approach 2:
The test structure itself provides the information needed for defect localization through its matrix configuration. The unique row and column signal combinations automatically identify which test unit contains a defect, making the system self-diagnosing without requiring external inspection tools or expert analysis.
3Adaptability or versatility
If multiple input/output pads are used for each test structure, then testing can be performed, but the number of pads increases device complexity and reduces wafer capacity
Solution Approach 1:
The matrix array structure provides universality where row signals and column signals serve multiple functions simultaneously. Each row signal can be combined with each column signal to address any test unit in the matrix, allowing fewer total pads while maintaining the ability to test multiple units. This multi-functional addressing scheme reduces the total pad count compared to dedicated pads for each test structure.
Solution Approach 2:
The patent transitions from a one-dimensional linear arrangement of test structures to a two-dimensional matrix array. This dimensional change allows addressing of N×M test units using only N+M signal lines instead of 2×(N×M) pads, significantly reducing the number of input/output pads required while maintaining full testing capability.
Data Source
AI summary
A device under test (DUT) array provides defect information rapidly and systematically. The DUT array includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the DUT array.