Duty Cycle Correction Amplifier With Buffered MOS Signal Stages
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Solution Overview
Problem
Conventional duty cycle correction amplification circuits face issues with reduced amplification factor and operating speed due to impaired voltage margins for NMOS differential input transistors and increased load capacitance, leading to distorted frequency characteristics.
Innovation Solution
The proposed duty cycle correction amplification circuit incorporates dual MOS differential input transistors and a duty cycle corrector that adjusts current to maintain higher voltage levels for NMOS transistors, improving operating characteristics and reducing load capacitance by connecting the duty cycle corrector in series with the second amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the duty cycle corrector is connected to the first and second preliminary signals to correct the duty cycle, then the duty cycle correction is achieved, but the voltage levels of the preliminary signals are reduced and the amplification factor decreases
Solution Approach 1:
The patent introduces a third amplifier as an intermediary component between the second amplifier and the duty cycle corrector. This third amplifier acts as a buffer that prevents the direct loading effect of the duty cycle corrector on the preliminary signals, thereby maintaining the voltage levels and amplification factor while still enabling duty cycle correction functionality.
Solution Approach 2:
The patent segments the amplification and correction functions into separate stages by adding a third amplifier. The first and second amplifiers handle signal amplification, while the third amplifier handles the duty cycle correction, allowing each component to operate optimally without interfering with the others' performance.
2Manufacturing precision
If the duty cycle corrector is connected to correct the duty cycle of preliminary signals, then the duty cycle is corrected, but the operating speed of the circuit decreases
Solution Approach 1:
The third amplifier serves as an intermediary that isolates the duty cycle corrector from the signal path, preventing the corrector's load capacitance from directly affecting the operating speed of the main amplification path. This allows duty cycle correction without significant speed penalty.
3Manufacturing precision
If the duty cycle corrector is connected to correct the duty cycle, then the duty cycle correction is achieved, but the load capacitance increases and frequency characteristics deteriorate
Solution Approach 1:
The third amplifier acts as a buffer that isolates the load capacitance of the duty cycle corrector from the preliminary signals. This intermediary stage prevents the corrector's capacitance from loading down the signal path, thereby maintaining good frequency characteristics while enabling duty cycle correction.
4Use of energy by moving object
If the circuit operates at lower voltages to improve energy efficiency, then power consumption is reduced, but the voltage margin for NMOS transistors is impaired and amplification factor decreases
Solution Approach 1:
By segmenting the circuit into separate amplification and correction stages with the third amplifier, the design allows operation at lower voltages for power efficiency while maintaining sufficient voltage margins in each stage. The isolated architecture prevents voltage degradation from propagating through the signal path.
Data Source
AI summary
A duty cycle correction amplification circuit is disclosed and comprises a first amplifier comprising dual first MOS differential input transistors gated respectively by first and second reference signals, and adapted to generate first and second preliminary signals, a second amplifier comprising dual second MOS differential input transistors respectively gated by first and second preliminary signals and adapted to generate first and second internal signals, and a duty cycle corrector adapted to correct a duty cycle associated with the first and second internal signals, wherein one of the first and second internal signals comprises an amplified output signal having a corrected duty cycle.