Duty-Cycle Phase Shift Circuit for Low-Power Clock Alignment
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Solution Overview
Problem
Conventional de-skew circuits in high-density multi-lane forwarded-clock links are power-hungry and inefficient in aligning received clocks with data, often relying on delay-locked loops and phase-locked loops which are not optimized for duty-cycle correction and phase shifting.
Innovation Solution
A duty-cycle corrector phase shift (DCCPS) circuit incorporating a voltage-controlled delay line, duty-cycle corrector, error amplifier, and digital-controlled delay line, along with DC sampler and lock detector circuits, to achieve a 50% duty cycle and precise phase shifts, such as 90 or 270 degrees, in clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay-locked loop and phase-locked loop are used in conventional de-skew circuits, then clock alignment with data is achieved, but power consumption increases
Solution Approach 1:
The patent combines duty-cycle correction and phase shifting functions into a single integrated DCCPS circuit, merging multiple functions that were previously handled by separate DLL/PLL circuits. This integration reduces the overall power consumption while maintaining clock alignment precision by eliminating redundant circuitry and optimizing the shared resource usage.
Solution Approach 2:
The DCCPS circuit serves multiple functions simultaneously: it performs duty-cycle correction to achieve 50% duty cycle, executes phase shifting to align clock with data, and provides de-skew functionality. This multi-functionality replaces the need for separate specialized circuits, reducing total power consumption while maintaining all required capabilities.
2Measurement precision
If conventional de-skew circuits are used, then clock and data alignment is achieved, but device complexity increases
Solution Approach 1:
The patent merges duty-cycle correction, phase shifting, and de-skew functions into a single DCCPS circuit module. This consolidation reduces device complexity by eliminating the need for multiple separate circuits (DLL, PLL, and duty-cycle correctors) and their associated control logic, while maintaining precise clock-data alignment through the integrated design.
3Use of energy by moving object
If duty-cycle corrector and phase shift circuit are integrated, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The DCCPS circuit incorporates feedback mechanisms where the DC sampler samples the output clock signal and feeds it back through the error amplifier to automatically adjust and maintain the 50% duty cycle and correct phase shift. This self-correcting capability compensates for manufacturing variations and precision errors, allowing the circuit to achieve accurate performance despite typical fabrication tolerances.
Solution Approach 2:
The circuit uses a feedback loop where the DC sampler monitors the output clock signal characteristics and the error amplifier adjusts the phase shifter and duty-cycle corrector accordingly. This feedback mechanism ensures that manufacturing imprecision does not degrade performance, as the circuit dynamically compensates for deviations from ideal parameters.
Data Source
AI summary
A duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. A duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. The DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.