Duty-Cycle Corrector Circuit for Clock Reactivation Stability
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Solution Overview
Problem
Existing duty-cycle correction methods in electronic devices are inadequate for maintaining a stable 50% duty-cycle of clock signals during operation, as they often saturate when the input clock signal is disabled, leading to distorted clock signals upon reactivation and potential loss of clock periods.
Innovation Solution
A duty-cycle corrector circuit that includes an integrator circuit, an amplifier circuit, and a clock detector, which measures and regulates duty-cycles in real-time and disables duty-cycle correction when the input clock signal is disabled, preventing saturation and ensuring accurate duty-cycle correction upon reactivation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If duty-cycle correction is continuously applied, then duty-cycle stability is improved, but saturation occurs when input clock is disabled causing distortion upon reactivation
Solution Approach 1:
The clock detector detects the disabled state of the input clock signal in advance and proactively disables the duty-cycle correction circuit before saturation can occur. This preliminary action prevents the harmful state from developing, ensuring that when the clock is reactivated, the correction circuit is already in a safe operating state and can immediately provide accurate correction without distortion.
Solution Approach 2:
The clock detector continuously monitors the input clock signal state and provides feedback to control the enable signal for the duty-cycle correction circuit. This feedback mechanism ensures that the correction circuit operates only when appropriate (when clock is active) and remains disabled when the clock is inactive, preventing saturation while maintaining stability during active operation.
2Use of energy by stationary object
If duty-cycle correction is enabled during clock disablement, then continuous regulation is maintained, but error signals saturate leading to loss of clock periods
Solution Approach 1:
The system takes preliminary action by detecting the clock disable state and disabling the correction circuit before saturation can occur. This prevents the condition that would lead to clock period loss upon reactivation, ensuring that the first clock periods after reactivation are not lost due to saturation effects.
Solution Approach 2:
The clock detector and control logic apply preliminary anti-action by preventing the duty-cycle correction circuit from operating during clock disablement. This counteracts the potential harmful effect of saturation before it can occur, eliminating the root cause of subsequent clock period loss rather than attempting to correct it after the fact.
3Measurement precision
If amplifier circuit gain is increased, then duty-cycle correction precision is improved, but saturation occurs more easily when clock is disabled
Solution Approach 1:
The clock detector enables preliminary detection of the disabled state, allowing the system to disable the amplifier circuit before high gain can cause saturation. This preliminary action protects the high-gain amplifier from operating in a saturated state, maintaining both precision during active operation and preventing harmful saturation during inactive periods.
Solution Approach 2:
The feedback mechanism through the clock detector continuously monitors clock signal presence and dynamically controls the amplifier enable state. This feedback ensures that high gain is applied only when the clock is active, maximizing measurement precision during operation while preventing saturation during disablement, thus resolving the contradiction between precision and saturation susceptibility.
Data Source
AI summary
Electronic devices for correcting a duty-cycle of a clock signal are disclosed. An electronic device may include circuitry configured to receive an input clock signal and generate, based on the input clock signal, a number of corrected clock signals. The circuitry may further be configured to generate, via an amplifier of the circuitry, a number of error signals based on the number of corrected clock signals and adjust a duty cycle of the number of corrected clock signals based on the number of error signals. Further, the circuitry may be configured to disable the amplifier in response to determining that the input clock signal is disabled. Associated apparatuses and methods are also disclosed.