Closed-Loop Duty Cycle Correction for High-Frequency Differential Signals
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Solution Overview
Problem
Conventional duty cycle correction circuits face accuracy issues in detecting small duty cycle differences, especially at high frequencies, leading to power consumption and reliability degradation due to clock jitter and inter symbol interference.
Innovation Solution
A duty cycle correction circuit with a duty cycle adjuster, lock signal generator, and correction bit generator, which iteratively adjusts differential input signals using correction bits and a closed-loop mechanism to achieve precise duty cycle correction, reducing power consumption by deactivating components when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional duty cycle correction circuit uses a comparator to detect small duty cycle differences, then the circuit can operate continuously to maintain duty cycle accuracy, but the power consumption increases significantly and the accuracy decreases at high frequencies
Solution Approach 1:
The duty cycle correction circuit performs correction operations periodically rather than continuously. The circuit includes a duty cycle correction unit that corrects duty cycle distortion based on a detection result, and the operation is triggered periodically or event-driven, allowing the circuit to remain in a low-power state during intervals between corrections while still maintaining duty cycle accuracy when needed.
2Measurement precision
If the comparator detects significantly small differences in charge stored in capacitors, then the duty cycle correction accuracy improves, but the comparator accuracy is affected and overall circuit accuracy degrades
Solution Approach 1:
The circuit performs preliminary duty cycle detection and correction operations before the distortion becomes significant. The duty cycle correction unit proactively adjusts the duty cycle based on detection results, preventing the accumulation of large distortions that would require the comparator to detect extremely small differences, thereby maintaining both accuracy and reliability.
Solution Approach 2:
The patent introduces intermediate processing stages between the capacitor charge storage and the final comparison operation. These intermediate stages include duty cycle detection units and correction units that process the signals in multiple steps, allowing the system to handle small duty cycle differences more effectively by breaking down the detection process into manageable stages rather than relying on a single comparator to detect all variations.
3Reliability
If the duty cycle correction circuit operates continuously as long as the SoC is operational, then the duty cycle remains corrected, but the power consumption increases significantly
Solution Approach 1:
The duty cycle correction circuit is designed to operate periodically rather than continuously. The correction unit is activated based on detection results or periodic triggers, allowing the circuit to maintain duty cycle correction reliability while consuming minimal power during idle periods when no correction is needed.
Solution Approach 2:
The circuit incorporates self-monitoring capabilities where the duty cycle detection unit continuously monitors the duty cycle status, and the correction unit is automatically activated only when distortion is detected. This self-service mechanism ensures reliable duty cycle maintenance while minimizing power consumption by avoiding unnecessary continuous operation.
Data Source
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AI summary
A duty cycle correction circuit (106) includes a duty cycle adjuster (108) that is configured to receive first and second differential input signals (D1, D2) having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals (O1, O2) having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits (B1-B4) that are generated based on a duty cycle detection signal (DS) that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal (LOCK) that is activated when the duty cycle detection signal toggles from one logic state to another.