Clock Duty Cycle Calibration Using Delay Matching and PLL Feedback
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Solution Overview
Problem
The stability of the clock duty cycle in reference clock signals is compromised by external interference, affecting the accuracy of clock duty cycle calibration circuits and phase-locked loop performance in wireless communication systems.
Innovation Solution
A clock duty cycle calibration circuit comprising a duty cycle calibration cell, delay matching cell, signal frequency multiplier cell, phase-locked loop cell, and calibration control cell, which work together to align and adjust the duty cycle of calibration clock signals to a target value, enhancing accuracy by compensating for duty cycle offsets due to temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock duty cycle calibration is performed using conventional methods, then the duty cycle can be adjusted, but the stability is compromised by external interference and temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where the calibrated clock signal is fed back through a phase-locked loop to continuously monitor and adjust the duty cycle. The PFD compares the phase of the divided feedback clock with the calibrated clock, and the D-type flip-flop samples the calibration clock signal at specific phases to generate correction signals that maintain stable duty cycle despite external interference
Solution Approach 2:
The calibration circuit performs self-correction by automatically detecting duty cycle deviations through the feedback loop and generating appropriate calibration control signals. The system uses its own output signal to monitor and adjust its performance, eliminating the need for external intervention to maintain duty cycle stability
2Measurement precision
If the frequency of the phase-locked loop reference clock signal is increased through clock multiplier technology, then the phase noise performance is improved, but the duty cycle stability becomes more critical
Solution Approach 1:
The patent performs duty cycle calibration before the clock signal enters the phase-locked loop and frequency multiplication stage. By pre-calibrating the reference clock signal to have accurate duty cycle, the subsequent frequency multiplication process maintains better phase noise performance without amplifying duty cycle errors
Solution Approach 2:
The feedback loop continuously monitors the calibrated clock signal and makes real-time adjustments to maintain duty cycle stability, ensuring that the high-frequency clock signals generated by frequency multiplication maintain their temporal accuracy and phase coherence
3Measurement precision
If duty cycle calibration is performed without considering temperature variations, then the circuit complexity is reduced, but the accuracy decreases due to temperature-induced offsets
Solution Approach 1:
The feedback mechanism continuously monitors the clock signal characteristics and automatically compensates for temperature-induced duty cycle offsets. The D-type flip-flop samples the clock signal at different phases and generates correction signals that counteract temperature variations, maintaining calibration accuracy across different operating conditions
Solution Approach 2:
The calibration control signal dynamically adjusts timing parameters based on temperature variations. By changing the phase sampling points and delay amounts in response to temperature changes, the system maintains accurate duty cycle calibration without requiring complex temperature sensing circuits
Data Source
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AI summary
A clock duty cycle calibration circuit, method, and clock multiplier circuit, wherein the clock duty cycle calibration circuit uses the calibration control cell to perform a first sampling process on the delay-matched clock signal using the first feedback clock signal when the phase-locked loop cell is in the first locked state, can acquire a first sampled signal that used to instruct the relationship between the actual duty cycle of the calibration clock signal and the target duty cycle, then the calibration control cell generates the first calibration control signal according to the first sampled signal, thereby enable the duty cycle calibration cell to maintain the duty cycle of the calibration control signal at the target duty cycle according to the first calibration control signal, that can overcome duty cycle offset caused by operating temperature, which helps improve the accuracy of the generated calibration clock signal.