Duty Cycle Correction in Divide-by-1.5 Frequency Divider Circuits
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Solution Overview
Problem
Existing frequency division circuits struggle to generate a decimal-frequency division signal with a duty ratio of 50% without using four-phase clocks.
Innovation Solution
A frequency division correction circuit comprising a voltage control oscillator, a divide-by-1.5 divider, a duty cycle corrector, and a divide-by-2 divider, which corrects the duty ratios of intermediate signals to achieve a 50% duty cycle before further frequency division, enabling the generation of four-phase clock signals with uniform phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If decimal frequency division is performed using conventional frequency dividing circuits, then frequency division output can be obtained, but the duty ratio cannot be maintained at 50%
Solution Approach 1:
The frequency division function is segmented into two independent parts: a first frequency divider that performs the decimal frequency division, and a separate duty ratio corrector that adjusts the output duty ratio to 50%. This segmentation allows each module to be optimized independently, achieving precise duty ratio control without significantly increasing overall circuit complexity.
Solution Approach 2:
A duty ratio corrector is introduced as an intermediary component between the frequency divider and the output. This corrector receives the frequency division output signal and actively adjusts its duty ratio to 50%, serving as a mediator that resolves the contradiction between maintaining simple circuitry and achieving precise duty ratio control.
2Manufacturing precision
If four-phase clocks are used to generate decimal-frequency division signals, then duty ratio of 50% can be achieved, but the device complexity increases
Solution Approach 1:
The patent extracts the duty ratio correction function from the complex four-phase clock generation system and implements it as a standalone corrector module. This extraction eliminates the need for generating and managing four-phase clocks, thereby reducing device complexity while maintaining the ability to produce 50% duty ratio signals.
Solution Approach 2:
Instead of changing the fundamental clock structure to four-phase, the patent changes the parameter being controlled by introducing a duty ratio corrector that specifically adjusts the duty ratio parameter. This parameter-based approach achieves the desired 50% duty ratio without the complexity of multi-phase clock generation.
3Device complexity
If conventional frequency dividing circuits are used, then circuit structure is simple, but uniform phase differences cannot be achieved
Solution Approach 1:
The duty ratio corrector serves as an intermediary that receives the frequency division output and actively adjusts both the duty ratio and phase characteristics. This mediator ensures uniform phase differences in the output signals without requiring complex phase generation circuitry, thus maintaining simple circuit structure while achieving precise phase control.
Data Source
Figure 1A~2B
Figure 3A~3B
Figure 4~5
AI summary
A frequency division correction circuit includes: a first frequency divider (302) configured to perform decimal frequency division (divide by 1.5) on an input signal and output a first frequency division signal (CK11) and a second frequency division signal (CK14) which are different from each other in duty ratio; and a corrector (303) configured to generate a first output signal (CK21) having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.