Duty Cycle Correction Circuit for Fast Locking and Stable Clocks

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Solution Overview

Problem

Existing electronic systems face challenges with long locking cycles, rigid circuit designs, limited frequency, and low stability in generating precise and stable clock signals with fixed duty cycles, particularly in high-frequency applications.

Innovation Solution

A device and method that utilize a duty cycle correcting circuit comprising a coarse adjustment delaying unit, a fine adjustment delaying unit, and a regenerating circuit to generate phase-shifting clocks, adjusting delays to achieve a fixed duty cycle with small jitter in rising and falling edges, using a combination of NAND gates and inverters to control the phase shifts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed duty cycle is needed for precise clock signal, then stability is improved, but locking cycle becomes long

Engineering Contradiction:
ImprovestabilityVSAvoidlocking cycle
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The duty cycle correction is segmented into two independent stages: coarse correction stage using first delay lines to achieve major duty cycle adjustments, and fine correction stage using second delay lines to achieve precise duty cycle tuning. This segmentation allows the system to lock quickly through coarse adjustment while maintaining stability through fine adjustment, thereby resolving the contradiction between long locking cycle and stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coarse correction stage performs preliminary duty cycle adjustment before the fine correction stage takes over. By pre-establishing the approximate duty cycle through coarse delay lines, the system reduces the time required for final precision locking, thus shortening the overall locking cycle while maintaining stable operation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If a fixed duty cycle is needed for precise clock signal, then stability is improved, but circuit design becomes rigid

Engineering Contradiction:
ImprovestabilityVSAvoidcircuit design flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The circuit employs controllable delay elements (such as variable delay lines or delay elements with adjustable propagation delay) that can be dynamically controlled through control signals. This allows the duty cycle to be adjusted in real-time without changing the physical circuit structure, making the circuit both stable (fixed duty cycle when needed) and adaptable (adjustable when needed).

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the propagation delay parameter of delay elements through control signals to achieve duty cycle adjustment. By varying the delay parameter rather than changing the circuit topology, the system maintains structural rigidity for stability while achieving operational flexibility through parameter modulation.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If a fixed duty cycle is needed for precise clock signal, then stability is improved, but frequency becomes limited

Engineering Contradiction:
ImprovestabilityVSAvoidfrequency
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

By segmenting the delay correction into coarse and fine stages with separate delay line sets, the system achieves accurate duty cycle correction with fewer total delay stages. This reduces the overall propagation delay and allows the circuit to operate at higher frequencies while maintaining stable duty cycle correction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coarse correction stage performs preliminary duty cycle adjustment, reducing the burden on the fine correction stage. This preliminary action allows the fine correction stage to use simpler, faster circuit elements that can operate at higher frequencies, thereby overcoming the frequency limitation.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If a fixed duty cycle is needed for precise clock signal, then stability is improved, but measurement precision of duty cycle becomes challenging

Engineering Contradiction:
ImprovestabilityVSAvoidduty cycle detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The invention introduces a duty cycle detection circuit as an intermediary that measures the actual duty cycle and feeds back to the control unit. This intermediary measurement mechanism enables precise monitoring and adjustment of the duty cycle, resolving the contradiction between maintaining stable fixed duty cycle and achieving measurement precision for correction.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The duty cycle detection circuit provides feedback information about the actual duty cycle to the control unit, which then adjusts the delay elements accordingly. This feedback mechanism ensures both stable operation (by maintaining the target duty cycle) and measurement precision (by continuously monitoring and correcting based on actual measurements).

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11757432B2Device and method of correcting duty cycle
Publication Date: 2023.09.12 AP MEMORY TECH (HANGZHOU) LTD CO
  • US11757432B2 patent drawing
  • US11757432B2 patent drawing
  • US11757432B2 patent drawing

AI summary

A device of correcting duty cycle includes: a duty cycle correcting circuit, a controller of the duty cycle correcting circuit and a duty cycle detecting circuit. The duty cycle correcting circuit generates a pair of phase-shifting clocks in accordance with a pair of complementary clocks and regenerates a regenerated clock in accordance with the pair of phase-shifting clocks. The controller of the duty cycle correcting circuit couples to the duty cycle correcting circuit. The duty cycle detecting circuit couples to the duty cycle correcting circuit and the controller of the duty cycle correcting circuit, and generates a detecting output to the controller of the duty cycle correcting circuit in accordance with a current duty cycle of the regenerated clock. The controller of the duty cycle correcting circuit controls the duty cycle correcting circuit in accordance with the detecting output to adjust the pair of phase-shifting clocks.