Duty-Cycle Phase Shift Circuit for Low-Power Clock De-Skew
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Solution Overview
Problem
Conventional de-skew circuits in high-density multi-lane forwarded-clock links face challenges in accurately aligning received clocks with data, particularly due to the power-hungry nature of delay-locked loop (DLL) and phase-locked loop (PLL) components, which are crucial for maintaining aggressive bandwidth demands.
Innovation Solution
A duty-cycle corrector phase shift (DCCPS) circuit is introduced, comprising a voltage-controlled delay line (VCDL) circuit, a duty-cycle corrector (DCC) circuit, an error amplifier circuit, and DC sampler circuits, which adjust the duty cycle and phase shift of input clock signals to achieve a 50% duty cycle and specific phase shifts like 90 or 270 degrees, thereby optimizing clock alignment without the power inefficiencies of traditional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay-locked loop (DLL) and phase-locked loop (PLL) are used in de-skew circuits, then clock alignment accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the operating parameters by using a duty-cycle corrector to force the clock signal to have a 50% duty cycle, and by controlling the phase shift to specific values (90 or 270 degrees). This parameter control enables accurate clock alignment without requiring the complex feedback mechanisms of DLL/PLL, thereby reducing power consumption while maintaining alignment accuracy
Solution Approach 2:
The patent extracts and removes the power-hungry DLL and PLL components from the de-skew circuit. Instead, it uses a simplified architecture with a duty-cycle corrector and phase shift circuit that achieves the same clock alignment function with significantly lower power consumption
2Measurement precision
If duty cycle and phase shift are precisely controlled, then clock alignment performance is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the clock alignment function into two independent stages: first, a duty-cycle corrector that forces 50% duty cycle, and second, a phase shift circuit that introduces controlled phase shifts (90 or 270 degrees). This segmentation simplifies the overall circuit design compared to a monolithic DLL/PLL while achieving precise clock alignment performance
Data Source
AI summary
One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.