32K DVB-T2 Symbol Interleaver Using LFSR Address Permutation
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Solution Overview
Problem
The existing DVB-T and DVB-H standards lack an efficient symbol interleaver for the 32 k mode, which is necessary for the DVB-T2 standard to provide an even sparser deployment of DVB transmitters in a single frequency network, requiring improved error correction coding performance due to correlated fading in terrestrial broadcast channels.
Innovation Solution
A data processing apparatus with a linear feedback shift register and permutation circuit that generates pseudo-random bit sequences and addresses for mapping input symbols onto OFDM sub-carrier signals, utilizing a specific generator polynomial and permutation order to achieve optimal interleaving across 32 k sub-carriers, allowing flexible switching between 2 k, 4 k, 8 k, and 32 k modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a symbol interleaver is provided for 32 k mode with 32768 sub-carriers, then the error correction coding performance is improved by maximizing separation of encoded symbols, but the device complexity increases due to the need for extended linear feedback shift register and permutation circuit
Solution Approach 1:
The address generation process is segmented into two distinct stages: first generating a pseudo-random bit sequence via linear feedback shift register, then applying permutation to the register contents. This segmentation allows each component to be optimized independently while maintaining overall system reliability for 32k mode interleaving.
Solution Approach 2:
The system employs dynamic configuration where the linear feedback shift register can be reconfigured with different generator polynomials and the permutation circuit can apply different permutation orders. This dynamic adaptability enables the same hardware structure to serve multiple DVB modes (2k, 4k, 8k, 32k) while maintaining optimal error correction performance for each mode.
2Adaptability or versatility
If the linear feedback shift register is extended to generate addresses for 32768 sub-carriers, then the adaptability to support 32 k mode is improved, but the loss of time increases due to the longer period required to generate all addresses
Solution Approach 1:
The system performs preliminary action by pre-generating and storing the permutation pattern in lookup tables during system initialization. This allows the runtime address generation to simply retrieve and apply pre-computed permutation values rather than calculating them in real-time, significantly reducing the time penalty associated with supporting 32k mode while maintaining full adaptability.
Solution Approach 2:
The patent replaces complex real-time permutation calculation mechanisms with pre-computed lookup tables stored in memory. This substitution transforms the time-consuming computational process into a fast memory retrieval operation, enabling support for 32768 sub-carriers without proportionally increasing address generation time.
3Manufacturing precision
If simulation analysis is performed to verify the generator polynomial and permutation order, then the manufacturing precision of the interleaver configuration is improved, but the loss of time increases due to extensive testing requirements
Solution Approach 1:
The patent applies partial verification by focusing simulation efforts on critical parameters only - specifically the generator polynomial coefficients and permutation order - rather than exhaustively testing all possible configurations. This targeted approach achieves sufficient manufacturing precision for the interleaver configuration while significantly reducing verification time compared to comprehensive testing.
Data Source
AI summary
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.