Dynamic Bias Voltage for Memory Erase Loop Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In memory devices, an imbalance in the ratio of erase pulses to program pulses can lead to electron or hole trapping, causing threshold voltage shifts, resulting in program inhibit problems and read failures due to unbalanced erase loop operations.
Innovation Solution
A dynamic bias voltage system that includes a monitor circuit to detect threshold voltage drift and adjust the voltage applied to buffer word lines based on the erase loop count, preventing further threshold voltage shifts by inhibiting the erase effect on non-data word lines and select gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If erase pulses are applied to data word lines to perform erase operations, then erased data is cleared from memory cells, but threshold voltage drift occurs in non-data word lines and select gates due to electron or hole trapping
Solution Approach 1:
The patent introduces buffer word lines as intermediary elements positioned between the select gates and data word lines. These buffer word lines act as mediators that absorb or redirect the harmful erase effects (electron or hole trapping) before they reach the select gates and data word lines, thereby protecting the threshold voltage stability of critical components while maintaining erase operation effectiveness.
Solution Approach 2:
The patent dynamically adjusts the voltage parameter applied to buffer word lines based on the erase loop count. By changing the voltage parameter adaptively during erase operations, the system optimizes the protection effect on select gates and data word lines, preventing threshold voltage drift while ensuring complete erase functionality across different operational stages.
2Productivity
If the ratio of erase pulses to program pulses becomes unbalanced, then erase operations can be performed efficiently, but electrons or holes become trapped in unintended locations causing program inhibit problems and read failures
Solution Approach 1:
Buffer word lines serve as intermediary structures that intercept and manage charge carriers (electrons or holes) during unbalanced erase-program operations. By positioning these buffer word lines between select gates and data word lines, the system prevents charge trapping in unintended locations, thereby eliminating program inhibit problems and read failures while maintaining efficient erase operation speeds.
Solution Approach 2:
The patent implements a feedback mechanism that monitors the erase loop count and dynamically adjusts the voltage applied to buffer word lines accordingly. This feedback control ensures that even when erase pulses significantly outnumber program pulses, the system adapts the buffer word line voltage to prevent charge trapping, maintaining both operational speed and accuracy.
3Device complexity
If a fixed voltage is applied to buffer word lines during erase operations, then the circuit design is simple, but threshold voltage drift cannot be effectively prevented under varying erase loop conditions
Solution Approach 1:
The patent transitions from a static fixed voltage approach to a dynamic voltage adjustment mechanism for buffer word lines. The voltage applied to buffer word lines is dynamically modified based on the erase loop count, enabling the system to adapt to varying operational conditions and effectively prevent threshold voltage drift while maintaining reasonable circuit complexity through systematic control.
Solution Approach 2:
The patent changes the voltage parameter of buffer word lines from a fixed value to a dynamically adjusted value based on erase loop count. This parameter change enables the system to maintain threshold voltage stability under varying erase conditions, transforming a simple but ineffective fixed voltage design into a more complex yet reliable adaptive voltage control system.
Data Source
AI summary
Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.