Dynamic Binary Translation for Legacy Code Compatibility

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Solution Overview

Problem

Existing methods for supporting old computer programs on new processors require significant engineering and monetary resources, especially when new hardware features are introduced, leading to startup latency and resource-intensive solutions.

Innovation Solution

A hardware and software co-designed dynamic binary translation method that optimizes code to utilize new instructions or hardware features without relying on operating system support, by identifying hotspots and transparently translating microcode to take advantage of wider registers and improved instructions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the underlying computer processor translates all executable codes to the instruction set provided by the underlying computer processor, then the code can run on the new processor, but severe startup latency occurs because the whole executable needs to be interpreted

Engineering Contradiction:
Improvecode compatibilityVSAvoidstartup latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent segments the translation process by identifying and translating only hotspots (performance-critical code regions) rather than the entire executable. The processor divides the program into static regions (translated once) and dynamic regions (translated on-demand), eliminating the need to interpret the whole executable and thus reducing startup latency while maintaining adaptability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary translation of hotspot regions before they are executed. The processor identifies hotspots during initial execution and translates them in advance, so that subsequent executions of these regions benefit from the optimized native code without incurring translation overhead during startup.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If hardware is used to re-optimize hotspots in programs, then performance can be improved, but significant hardware resources are required (e.g., store-order preserving re-order buffer based atomicity model)

Engineering Contradiction:
ImproveperformanceVSAvoidhardware resources
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling the processor to automatically identify and translate its own hotspot regions without external intervention. The processor monitors its own execution patterns, detects performance-critical regions, and triggers translation autonomously, eliminating the need for complex external hardware support structures.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the operational parameters of the processor by introducing dynamic translation capabilities that adapt to execution patterns. The processor modifies its behavior based on runtime observations, switching between static and dynamic translation modes, and adjusting translation granularity to optimize performance without requiring significant additional hardware resources.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If the operating system enables support for new features/instructions, then the new hardware features can be utilized, but a lot of engineering resources and monetary resources are required

Engineering Contradiction:
Improvenew feature supportVSAvoidengineering resources
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a binary translation layer as an intermediary between legacy executables and the new processor instruction set. This translation layer handles the complexity of feature support and instruction set translation, allowing the operating system to remain unchanged while still enabling new hardware features to be utilized by old programs.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the complexity of OS support by moving the translation functionality into the processor itself. Rather than requiring the operating system to manage feature compatibility, the processor independently handles translation of legacy code, freeing the OS from this burden and reducing the engineering resources needed.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9417855B2Instruction and logic to perform dynamic binary translation
Publication Date: 2016.08.16 INTEL CORP
  • US9417855B2 patent drawing
  • US9417855B2 patent drawing
  • US9417855B2 patent drawing

AI summary

A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.