Dynamic Bus Clock Scaling for Power-Performance Tradeoffs
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Solution Overview
Problem
Conventional Dynamic Voltage and Frequency Scaling (DVFS) techniques primarily focus on CPU activity, leading to degraded performance in digital systems with master modules requiring independent bus bandwidth, as they do not effectively manage bus clock frequency based on the usage of on-chip buses.
Innovation Solution
An apparatus and method that dynamically scale the bus clock frequency by determining activity information of master modules, using a bus frequency controller to adjust the clock frequency based on whether a master module is using the bus, thereby optimizing power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DVFS technique is used to reduce power consumption by changing CPU frequency, then power consumption of CPU is reduced, but performance of digital system is degraded when master modules require independent bus bandwidth
Solution Approach 1:
The patent segments the frequency control into two independent parts: CPU frequency control and bus clock frequency control. The bus frequency controller independently manages bus clock frequency based on bus activity information from multiple master modules, while the CPU frequency can be controlled separately based on CPU activity. This segmentation allows the bus to maintain higher frequency when needed by master modules even when CPU frequency is reduced for power savings.
Solution Approach 2:
The patent implements dynamic bus clock frequency adjustment by continuously monitoring bus activity information from multiple master modules. The bus frequency controller dynamically changes the bus clock frequency in real-time based on the aggregate activity level, allowing the system to adapt bus performance to actual usage patterns rather than using a fixed or CPU-centric frequency control approach.
2Productivity
If fixed bus clock frequency is used to ensure system performance, then data transmission speed is maintained, but power consumption increases
Solution Approach 1:
The patent replaces fixed bus clock frequency with dynamic frequency adjustment based on real-time bus activity monitoring. The bus frequency controller continuously evaluates activity information from master modules and adjusts the bus clock frequency accordingly, maintaining high frequency when bus activity is high and reducing frequency when bus activity is low, thus optimizing the power-performance tradeoff.
Solution Approach 2:
The patent changes the bus clock frequency parameter dynamically based on bus activity conditions. By monitoring activity information from multiple master modules and adjusting the frequency parameter in response to changing usage patterns, the system adapts power consumption to actual performance requirements rather than maintaining a constant high frequency.
Data Source
AI summary
An apparatus and a method for scaling a dynamic bus clock are provided. The apparatus for scaling the dynamic bus clock includes at least one master module, at least one slave module, a bus for delivering data transmitted and received by the at least one master module and the at least one slave module, a bus frequency controller for determining a bus clock frequency by considering activity information of the at least one master module, and a clock generator for generating the frequency as determined by the bus frequency controller and providing the generated frequency to the at least one master module, the at least one slave module, and the bus.