DRAM Boosted Voltage Producer with Dynamic Charge Pump Control
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face inefficiencies in power consumption due to over-pumping during variable refresh times, as existing internal voltage supplies are configured for the worst-case scenario, leading to excessive current usage and higher power consumption, especially in smaller DRAM sizes with shorter and more variable refresh periods.
Innovation Solution
A boosted voltage producer using charge pump circuitry with capacitive elements, activated by control signals to provide a boosted voltage tailored to specific refresh times, allowing for adjustable voltage and current supply based on the DRAM's refresh mode, reducing unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the internal voltage supply is configured for the worst-case scenario (shortest refresh time), then the DRAM can handle the fastest refresh rates, but power consumption increases due to over-pumping during longer refresh times
Solution Approach 1:
The charge pump circuit is designed with dynamically controllable operation modes that adapt to different refresh time requirements. The circuit can switch between first and second operation modes based on the actual refresh time needed, allowing the voltage supply to match the specific requirements of each refresh operation rather than always operating at maximum capacity
Solution Approach 2:
The charge pump circuit changes its operating parameters (such as pumping current and voltage boost level) based on the refresh time mode. By detecting whether a first or second refresh time mode is required, the circuit adjusts its pumping characteristics to provide exactly the right amount of current and voltage boost needed, avoiding both under-pumping and over-pumping conditions
2Reliability
If the refresh time period is reduced to handle faster refresh rates, then data retention is improved, but the current boost requirement increases leading to higher power consumption
Solution Approach 1:
The voltage supply system dynamically adjusts its current boost capability based on the actual refresh time mode detected. When operating in the first refresh time mode (shorter period), the circuit provides higher current boost; when in the second refresh time mode (longer period), it reduces the current boost level, thereby maintaining data retention reliability while optimizing power consumption
3Ease of operation
If the charge pump circuit operates at maximum capacity for all refresh times, then the shortest refresh times are handled correctly, but longer refresh times result in over-pumping and inefficient power use
Solution Approach 1:
The charge pump circuit incorporates feedback mechanisms that monitor the actual refresh time mode being executed. Based on this feedback, the circuit adjusts its pumping activity to match the real-time requirements, preventing over-pumping during longer refresh intervals while ensuring adequate performance during shorter refresh intervals
Solution Approach 2:
Instead of always operating at maximum capacity, the charge pump circuit applies partial action by reducing its pumping effort when the refresh time mode indicates it is sufficient. This allows the circuit to use only the necessary amount of pumping power for each specific refresh operation, eliminating the excessive energy waste that would occur with constant maximum operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution optimizes power usage by dynamically adjusting the voltage and current supply according to the DRAM's refresh time, reducing power consumption and enhancing efficiency by matching the voltage boost to the specific requirements of the DRAM, thereby minimizing over-pumping and energy waste.
Implementation Method 1
each of the plurality of charge pump circuitry including a capacitive element. When charge pump circuitry is activated in response to a respective control signal, the capacitive element of the activated charge pump circuitry is charged in response to at least one of the input voltage and the charge pump signal, the charges of the activated charge pump circuitry contributing to provide the boosted voltage.
Data Source
AI summary
A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.