Apparatus Without Intermediate Ac Conversion TRIZ Cases

A double-gate charge pump circuit uses synchronized control signals to adjust transistor threshold voltages.

A PMIC boot timing circuit uses a triode to switch capacitors in parallel for flexible voltage threshold adjustment.

A negative voltage generator uses switch control to produce output without level shifters.

A power converter uses flying capacitors and switch networks to achieve extended output-to-input voltage conversion ratios.

Input and output status detection circuits feed a logic block that delays the reset signal, resolving complexity in integrated charge pump designs.

Dynamic switch networks in this bipolar charge pump circuit adapt topology to generate multiple voltage levels, reducing power loss and extending battery life.

A power converter adjusts control loop bandwidth dynamically using a functional block that scales the error signal based on voltage differences.

A charge pump gate drive circuit boosts the gate voltage to increase turn-on current in silicon carbide power switches.

A nine-level switched-capacitor multilevel inverter circuit achieves self-voltage balancing and boosting with reduced component count.

A hybrid dual-phase step-up power converter shares components between boost and charge pump stages to increase the voltage conversion ratio.

A SIDO buck converter supplies opposite polarity currents to recycle charge between outputs.

A backlight driver circuit adjusts gate drive voltage for MOSFETs in boost converters based on load conditions.

A replica device mirrors pass transistor behavior to stabilize LDO feedback loops.

A trimming circuit generates a reference voltage adjusted by code values while an internal voltage generation circuit divides and compares voltages based on operation modes.

Segmenting the single output capacitor into multiple parallel units reduces voltage ripple and recovery time while maintaining circuit stability.

Two out-of-phase sawtooth ramps define the buck-boost transition level, eliminating loop instability during mode switching.

An auto-tuning DC-to-DC controller eliminates overshoot and undershoot by measuring inductive energy error instead of relying on direct load current sensing.

A power management circuit generates a time-variant average power tracking voltage to optimize energy usage.

Segmented regulation reduces current overhead in image sensors by lowering noise amplification during charging.

Synchronous bulk voltage switching in HVPMOS charge pumps eliminates dynamic current losses and reduces on-resistance.

Poly-phase clocking shifts electrical spurs beyond natural roll-off points, reducing feed-through amplitude without adding decoupling capacitors.

Adaptive dead-time circuits and switching body biasing minimize reverse current in low voltage charge pumps, resolving leakage versus conduction trade-offs.

Multiple conversion branches enable wide range output voltage while maintaining high efficiency through dynamic branch control.

Configuring the capacitor equivalent series resistor larger than the battery internal resistance reduces dynamic response effects and extends cycle life.

Pump controller adjusts drivability based on target voltage levels, reducing power consumption in semiconductor devices.

A voltage pumping device adjusts oscillator pulse periods to maintain constant high voltage levels.

Staggered asynchronous voltage generation segments current draw from the external source, preventing peak level drops and minimizing electrical noise.

A voltage boosting system regulates output using a controlled clock frequency.

Alternating bootstrap capacitor voltage between high-side primary switches ensures full gate drive across varying duty cycles.

A voltage multiplier circuit uses a shared bulk node and bias generator to enable dual-mode operation.

A single inductor voltage regulation circuit sequences output control switches to maintain constant output voltages across multiple loads.

Dynamic clock frequency and amplitude adjustment based on load current maintains output voltage stability under high loading conditions.

Voltage detector circuits compare terminal voltages to thresholds, enabling controller detection of open or short circuits regardless of load current direction.

Feedback control adjusts switch states based on detected voltage differences to prevent over-voltage damage when inductor size is reduced.

Helper circuits distributed along word lines reduce effective length and RC delays, improving memory operation efficiency without adding decoding overhead.

A voltage generator uses a comparator and amplifier to switch between high and low ramp rates for rapid charging.

Master regulator distributes phase offset signals to controlled POL regulators, reducing peak input current and radiated emissions.

Interleaved reversible DC-DC converters operate at variable frequencies to supply vehicle on-board networks.

A multiple-phase switched-capacitor-inductor boost converter segments voltage stress across parallel circuits to enable high boost ratios with lower-voltage switches.

Segmented capacitors and dynamic switchgear control increase rail voltage while reducing switching losses caused by duty cycle limits.

Binary weighted segments in a segmented insulated gate power device reduce switching losses at low loads while minimizing conduction losses at high currents.

A switched capacitor power converter shares output with voltage regulator phases to generate required output voltage from input voltage.

Hardware abstraction layer inhibits watchdog disable pin to transition DC-DC voltage converter to safe mode.

Phase shift and delta duty control regulate capacitor voltage independently of power direction, reducing breakdown voltage requirements.

Capacitor decouples control side from high voltage switch, eliminating isolated drivers and reducing system cost.

A magnetic drive coupling transmits torque between rotatable shafts using magnetically attractive parts to replace mechanical seals.

Dynamic back-gate biasing in FDSOI transistors reduces conduction losses and boosts maximum output voltage by eliminating the bulk CMOS back-gate effect.

Dynamic charge pump circuits adapt voltage output to specific DRAM refresh times, eliminating over-pumping and reducing power consumption during sleep modes.

A boosted voltage generator circuit maintains constant on resistance in switched capacitor feedback switches using dynamic precharge.

An adaptive constant on time converter adjusts switching frequency using input and output voltage signals to regulate power delivery.