PMIC Boot Timing Circuit Using Capacitor Parallel Switching
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Solution Overview
Problem
Current PMIC boot timing control methods are challenging due to varying voltage and timing requirements for different timing control circuits, especially since PMICs lack internal non-volatile storage, making it difficult to achieve consistent boot timing without an internal code.
Innovation Solution
A PMIC boot timing circuit comprising a PMIC, capacitors, and a triode, where buck modules generate multiple voltages, and the triode controls capacitor connections in parallel to adjust voltage thresholds, enabling flexible timing generation and normal boot sequences without relying on non-volatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If PMIC omits internal non-volatile storage device to streamline the structure, then device complexity is reduced, but the ability to store internal code and achieve consistent boot timing is lost
Solution Approach 1:
The patent extracts the non-volatile storage function from the PMIC and relocates it to an external NVM device. The PMIC retains only the essential power management functions while the timing control circuit handles code retrieval from external memory, achieving structure simplification without sacrificing boot timing reliability.
Solution Approach 2:
The patent introduces a timing control circuit as an intermediary between the PMIC and external NVM. This mediator manages the boot sequence by controlling voltage generation, coordinating data transfer from external memory to PMIC, and ensuring proper timing synchronization, thereby compensating for the removed internal storage.
2Adaptability or versatility
If different timing control circuits have different voltage and timing requirements, then adaptability to various circuits is improved, but the difficulty of achieving universal control method increases
Solution Approach 1:
The patent configures different capacitance values for specific timing control circuits based on their individual requirements. Each circuit receives customized timing parameters through its local capacitor configuration, allowing the same PMIC to adapt to multiple circuit types without complex control logic.
Solution Approach 2:
The patent achieves adaptability by changing the capacitance parameter of the timing capacitor. Different capacitance values directly affect the RC time constant, thereby adjusting the boot timing to match different timing control circuit requirements. This simple parameter adjustment provides versatility without increasing control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the generation of different timing requirements and normal boot sequences by adjusting voltage thresholds, ensuring the entire panel operates correctly, eliminating the need for internal non-volatile memory devices in PMICs.
Implementation Method 1
the first buck module generates a first voltage
Implementation Method 2
the second buck module generates a second voltage
Implementation Method 3
the third buck module generates a third voltage
Implementation Method 4
the direct current source charges the first capacitor to a first voltage threshold
Implementation Method 5
the direct current source charges the first capacitor and the second capacitor to a second voltage threshold
Data Source
AI summary
The present disclosure provides a PMIC boot timing circuit and a PMIC boot timing determination method. The circuit includes a PMIC, a first capacitor, a second capacitor, and a triode, wherein the PMIC includes a first buck module, a second buck module, a third buck module and a direct current source; one end of the first capacitor is connected to the direct current source, and the other end of the first capacitor is grounded; one end of the second capacitor is connected to one end of the direct current source, and the other end of the second capacitor is connected to the drain of the triode; the source of the triode is grounded, and the gate of the triode is connected to the PMIC. Compared with the related art, the circuit and the method provided by the present disclosure can achieve different timing generation and normal boot timing.