Voltage Multiplier Circuit Common Bulk Biasing

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Solution Overview

Problem

Existing voltage multiplier circuits require significant integrated circuit area and suffer from parasitic capacitance due to multiple isolated P-type wells, which can lead to bulk charging issues and increased area occupation.

Innovation Solution

A voltage multiplier circuit design where all n-channel transistors share a common bulk not tied to any source, with a bias generator circuit applying a lower voltage to this common bulk, reducing area usage and parasitic capacitance by using triple well technology and a cross-coupled bias circuit configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple isolated P-type wells are used for each transistor bulk, then transistor isolation and individual biasing are achieved, but integrated circuit area increases and parasitic capacitance increases

Engineering Contradiction:
Improvetransistor isolationVSAvoidintegrated circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Multiple isolated P-type wells are merged into a single common bulk structure that serves all n-channel transistors. This consolidation reduces the total area occupied by bulk structures while maintaining proper transistor isolation through the shared bulk region, directly resolving the contradiction between isolation reliability and area efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The common bulk structure performs multiple functions simultaneously: it provides isolation for all n-channel transistors, serves as a shared biasing node, and reduces overall device area. This multi-functional design eliminates the need for separate isolated wells for each transistor, addressing both the reliability requirement and area reduction goal.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple isolated P-type wells are used for each transistor bulk, then individual bulk biasing is achieved, but parasitic capacitance increases

Engineering Contradiction:
Improvebulk biasing controlVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

Multiple isolated bulk structures are combined into a single common bulk, reducing the total parasitic capacitance associated with bulk nodes. The merged structure presents a smaller total capacitance to the circuit while still providing adequate biasing control for all transistors, thus reducing the harmful capacitive effects.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The individual bulk biasing control is extracted from separate isolated wells and consolidated into a unified common bulk biasing scheme. This extraction eliminates the redundant capacitance of multiple separate bulk nodes while preserving the essential bulk biasing function through the single common structure.

Inventive Principle:
Principle #2Taking out (Extraction)

3Area of stationary object

If common bulk is shared by all transistors, then area is reduced and parasitic capacitance is minimized, but bulk charging issues may occur

Engineering Contradiction:
Improveintegrated circuit areaVSAvoidbulk charging stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

A dedicated bulk biasing circuit is introduced as an intermediary between the power supply and the common bulk. This intermediary circuit actively manages the bulk voltage, preventing charging issues while maintaining the area benefits of the common bulk structure. The biasing circuit serves as a mediator that ensures stable bulk operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The bulk biasing circuit incorporates feedback mechanisms that monitor and adjust the common bulk voltage to prevent charging issues. This feedback control ensures that the common bulk operates at the correct potential despite variations in circuit conditions, maintaining reliability while preserving area reduction benefits.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11183924B2Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation
Publication Date: 2021.11.23 STMICROELECTRONICS INT NV
  • US11183924B2 patent drawing
  • US11183924B2 patent drawing
  • US11183924B2 patent drawing

AI summary

A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.