Dynamic Clock Frequency Control for Power-Performance Trade-offs

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Solution Overview

Problem

Portable multimedia devices face a trade-off between increased clock frequency for performance and higher power consumption, necessitating an efficient method to control clock speeds selectively.

Innovation Solution

A method and system that monitor master devices on a bus, adjust clock frequency based on requests, preferences, and activity levels, using a programmable clock controller to vary the clock frequency in response to trigger inputs, thereby optimizing performance and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the clock frequency is increased to improve performance and provide quicker access to stored files, then the performance is improved, but the power consumption increases

Engineering Contradiction:

ImproveperformanceVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The clock frequency is made dynamic rather than fixed. The system automatically adjusts the clock frequency between different levels (e.g., first clock frequency and second clock frequency) based on real-time detection of device activity states, allowing the device to optimize between performance and power consumption adaptively

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter based on detected activity states. When high activity is detected, the system switches to a higher clock frequency to improve performance; when low activity is detected, it switches to a lower clock frequency to reduce power consumption, thereby resolving the contradiction between performance and energy efficiency

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7725759B2System and method of managing clock speed in an electronic device

Publication Date: 2010.05.25 VLSI TECHNOLOGY LLC

AI summary

A method of controlling a clock frequency is disclosed and includes monitoring a plurality of master devices that are coupled to a bus within a system. The method also includes receiving an input from at least one of the plurality of master devices. The input can be a request an increase to the clock frequency of the bus. Further, the method includes selectively increasing the clock frequency of the bus in response to the request.