Dynamic Clock Tree Planning With Feed-Timing Cost Balancing
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Solution Overview
Problem
Conventional clock tree planning systems do not adequately consider the number of feedthroughs in clock tree topologies, leading to suboptimal circuit designs that may compromise existing layouts or require undesirable changes, and the impact of timing and feedthroughs is not accurately separated.
Innovation Solution
Implementing a feed-timing cost parameter as a vector of path-length and feedthrough count to generate multiple clock tree topologies, allowing users to balance timing and feedthroughs, presented through a graphical interface for selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock tree planning is used, then timing optimization is achieved, but feedthrough count is not adequately considered leading to suboptimal circuit designs
Solution Approach 1:
The patent applies parameter changes by introducing a feed-timing cost parameter that combines timing cost and feedthrough count into a unified metric. This allows the clock tree planning to optimize based on both timing and feedthrough considerations simultaneously, rather than treating them as separate conflicting parameters. The cost parameter is dynamically adjusted during the planning process to balance timing optimization with feedthrough reduction.
Solution Approach 2:
The patent implements feedback by continuously evaluating the feed-timing cost during clock tree planning iterations and using this evaluation to guide subsequent planning decisions. The system monitors both timing performance and feedthrough count, and adjusts the clock tree topology based on this feedback to achieve optimal balance between the two parameters.
2Stability of the object's composition
If feedthrough count is reduced, then circuit layout integrity is maintained, but timing performance may be compromised
Solution Approach 1:
The patent transforms the trade-off between layout integrity and timing performance into a unified optimization problem by using the feed-timing cost parameter. This parameter dynamically weights the importance of timing versus feedthrough count, allowing the system to find solutions that maintain layout integrity while achieving acceptable timing performance, or prioritize timing when necessary.
Solution Approach 2:
The patent applies dynamics by making the optimization criteria adaptive rather than static. The feed-timing cost parameter is adjusted during the planning process based on current performance metrics, allowing the system to dynamically balance between maintaining layout integrity and achieving timing performance. This enables flexible adaptation to different design priorities.
3Adaptability or versatility
If multiple clock tree topologies are generated, then design flexibility is improved, but processing resources increase
Solution Approach 1:
The patent uses parameter changes to control the generation of clock tree topologies by adjusting the feed-timing cost threshold. By dynamically setting thresholds for when to generate additional topologies versus when to accept the current best solution, the system balances design flexibility with processing resource consumption. The parameter adjustment allows selective exploration of the solution space.
Data Source
AI summary
A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.