Dynamic Deep N-Well Isolation for NMOS Parasitic Capacitance Reduction
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Solution Overview
Problem
The existing circuit structures using deep n-wells for NMOS transistors suffer from non-linear parasitic capacitances at the borders between p-wells and deep n-wells, which can lead to increased noise and deleterious effects on circuit performance due to electrical coupling and signal distortion.
Innovation Solution
The implementation of a circuit structure with an NMOS transistor having its drain and source in a p-well above a deep n-well, where the deep n-well is connected to a predetermined voltage during an enable phase and electrically floats during a non-enable phase, and the p-well is connected to the source of the NMOS transistor, effectively configuring the parasitic capacitances to appear in series, reducing the overall non-linear capacitance at the input node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If deep n-wells are used to isolate NMOS transistors, then electrical coupling and noise are reduced, but non-linear parasitic capacitances are formed at the borders between p-wells and deep n-wells
Solution Approach 1:
The patent extracts the harmful parasitic capacitances from the signal path by dynamically disconnecting the deep n-well from the signal node during the non-enable phase. This temporal separation removes the parasitic capacitance effect when it would otherwise interfere with signal processing, while maintaining the isolation benefits during the enable phase.
Solution Approach 2:
The patent applies dynamic switching of the deep n-well connection state between enabled and disabled phases. By making the n-well connection dynamic rather than static, the circuit can optimize performance during different operational phases, reducing parasitic capacitance effects during critical signal processing while maintaining isolation when not actively processing signals.
2Object-affected harmful factors
If deep n-wells are used to isolate NMOS transistors, then noise is reduced, but circuit performance deteriorates due to signal distortion from parasitic capacitances
Solution Approach 1:
The patent employs periodic switching of the deep n-well connection in synchronization with the circuit's operational phases. During the enable phase, the n-well is connected to provide isolation; during the non-enable phase, it is disconnected to eliminate parasitic effects. This periodic action ensures that noise reduction and signal integrity are both maintained at different times in the operational cycle.
Solution Approach 2:
The patent preliminarily disconnects the deep n-well from the signal node before the critical signal processing occurs during the non-enable phase. This preliminary action prevents the parasitic capacitances from being present when they would cause signal distortion, proactively eliminating the problem before it can affect circuit performance.
3Stability of the object's composition
If the deep n-well is continuously connected to a fixed voltage, then isolation is maintained, but non-linear parasitic capacitance affects the input node
Solution Approach 1:
The patent transforms the static deep n-well connection into a dynamic one that switches between connected and disconnected states. During the enable phase, the n-well is connected to maintain isolation stability; during the non-enable phase, it is disconnected to eliminate parasitic capacitance effects at the input node. This dynamic approach resolves the contradiction between maintaining stable isolation and eliminating parasitic effects.
Solution Approach 2:
The patent extracts the parasitic capacitance from the input node by dynamically disconnecting the deep n-well during the non-enable phase. This temporal extraction removes the harmful parasitic effect from the input node when it would otherwise interfere with signal processing, while maintaining the isolation benefits during the enable phase when the connection is active.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the non-linear parasitic capacitance at the input node, improving circuit response and reducing signal distortion by dominating the capacitance value with the smaller of the two capacitances in series, thereby enhancing circuit performance.
Implementation Method 1
parasitic capacitances are formed at the border between the p-well and deep n-well, as well as at the border between the deep n-well and the p-well
Data Source
AI summary
A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.