Dynamic Deep Depletion FET for Low On-Resistance
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Solution Overview
Problem
Enhancement trench type power MOSFETs face high on-resistance (RDSON) due to low impurity concentration in mesa regions and body below trenches, which limits blocking voltage and increases device resistance.
Innovation Solution
A buried insulated gate JFET with dynamically created overlapping depletion regions between trenches, achieved by pulsing spaced gates to extend depletion width beyond the threshold voltage, allowing higher epi concentration and reduced RDSON while maintaining high blocking voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If low impurity concentration is used in mesa regions and body below trenches, then blocking voltage is improved, but on-resistance increases
Solution Approach 1:
The patent employs dynamic depletion regions created by pulsing the gates to temporarily extend the depletion width beyond the threshold voltage. This dynamic approach allows the device to achieve low on-resistance during conduction while maintaining high blocking voltage when the depletion regions are extended through pulsing, resolving the contradiction between low impurity concentration benefits and resistance issues.
Solution Approach 2:
The patent changes the doping concentration parameter in the epi layer from low to high (higher epi concentration), which reduces on-resistance. Simultaneously, it uses gate pulsing to dynamically extend depletion regions to maintain the high blocking voltage capability, thus resolving the contradiction between blocking voltage and on-resistance.
2Reliability
If higher epi concentration is used, then on-resistance is reduced, but blocking voltage capability deteriorates
Solution Approach 1:
By using dynamic gate pulsing, the depletion regions are temporarily extended beyond the threshold voltage to achieve high blocking voltage capability. This allows the device to use higher epi concentration for low on-resistance while maintaining blocking voltage performance through the dynamic depletion extension mechanism.
Solution Approach 2:
The patent employs periodic pulsing of the gates to create dynamic depletion regions that extend the blocking capability. This periodic action allows the device to switch between low-resistance conduction state and high-blocking-voltage state, resolving the contradiction between using higher epi concentration and maintaining blocking voltage.
3Reliability
If conventional trench MOSFET structure is used, then device performance is achieved, but process complexity increases due to body contact requirements
Solution Approach 1:
The patent removes the body contact requirement from the conventional trench MOSFET structure. By using the dynamic depletion mechanism extending from the trench gates, the device achieves the necessary blocking and conduction control without requiring separate body contacts, thus simplifying process integration while maintaining device performance.
Solution Approach 2:
The trench gates in the patent serve multiple functions: they control the channel conduction and simultaneously create the dynamic depletion regions that provide blocking voltage. This multi-functionality eliminates the need for separate body contacts, reducing device complexity while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dynamic deep depletion FET (DDDFET) achieves lower RDSON, higher cell density, and faster switch speed by utilizing higher epi doping without increasing on-resistance, and simplifies process integration by eliminating the need for body contacts.
Implementation Method 1
spaced gates are pulsed, producing overlapping depletion regions in the mesas between gate trenches. This then permits reduced RDSON because the dynamic mode turn off permits a higher epi concentration in the silicon base while still blocking the current along the channel.
Implementation Method 2
This device takes advantage of the known phenomenon that the depletion region at a MOS gate extends momentarily (tens of milliseconds) well beyond Wd at the threshold voltage.
Data Source
AI summary
A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.