Dynamic DLL Phase-Chasing with Adaptive Frequency Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay locked loop (DLL) circuits face reduced efficiency and stability due to the use of fixed frequency divisors, which either slow down phase-chasing speed or reduce steadiness, as they either divide the clock signal too much or not enough.
Innovation Solution
A DLL circuit with a dynamic phase-chasing function, incorporating a divisor-adjustable frequency-dividing circuit that detects the overall loop delay to determine an optimal divisor, allowing for dynamic adjustment of frequency division during the phase-locking period to enhance both speed and steadiness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a frequency divider with a fixed divisor is used to improve steadiness, then the steadiness of the DLL circuit is improved, but the phase-chasing speed is reduced
Solution Approach 1:
The patent applies the dynamics principle by making the divisor of the frequency divider adjustable rather than fixed. The divisor is dynamically changed based on the operating state of the DLL circuit: using a first divisor value during phase-chasing to maximize speed, and a second divisor value during phase-locking to maximize steadiness. This dynamic adjustment resolves the contradiction between speed and stability by adapting the system parameters to different operational requirements.
Solution Approach 2:
The patent implements periodic action by dividing the operation of the DLL circuit into distinct phases: a phase-chasing period and a phase-locking period. During the phase-chasing period, the frequency divider uses a divisor optimized for speed; during the phase-locking period, it switches to a divisor optimized for steadiness. This periodic switching of operational modes allows the system to achieve both high phase-chasing speed and high steadiness at different times, resolving the contradiction.
2Stability of the object's composition
If the divisor of the frequency divider is increased to improve steadiness, then the steadiness is improved, but the efficiency of the DLL circuit is reduced
Solution Approach 1:
The patent applies dynamics by making the divisor adjustable based on operational needs. During phase-chasing, a smaller divisor is used to maintain high efficiency and fast response. During phase-locking, a larger divisor is used to improve steadiness. This dynamic adjustment ensures that the system achieves high efficiency during critical timing acquisition while maintaining steadiness during normal operation, resolving the contradiction between efficiency and steadiness.
Solution Approach 2:
The patent uses periodic action by structuring the operation into phases where efficiency is prioritized during phase-chasing and steadiness is prioritized during phase-locking. The frequency divider switches between different divisor values periodically according to the operational phase, allowing the system to achieve both high efficiency and high steadiness at appropriate times, thus resolving the contradiction.
3Speed
If the divisor of the frequency divider is decreased to improve phase-chasing speed, then the phase-chasing speed is improved, but the steadiness of the DLL circuit is reduced
Solution Approach 1:
The patent applies the dynamics principle by making the divisor adjustable rather than fixed. During the phase-chasing period, a smaller divisor is used to maximize phase-chasing speed. During the phase-locking period, a larger divisor is used to maximize steadiness. This dynamic adjustment based on operational state resolves the contradiction by allowing the system to optimize for speed when needed and for stability when needed.
Solution Approach 2:
The patent implements periodic action by dividing operation into phase-chasing and phase-locking periods. During the phase-chasing period, the divisor is set to a value optimized for speed; during the phase-locking period, it switches to a value optimized for steadiness. This periodic switching allows the system to achieve both high phase-chasing speed and high steadiness at different times, resolving the contradiction.
Data Source
AI summary
A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.