Dynamic Electrostatic Doping in FETs for Short-Channel Control
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Solution Overview
Problem
As transistors approach nanoscale dimensions, short-channel effects and subthreshold slope degradation hinder further scaling, leading to increased off-state leakage current and reduced efficiency in switching between on and off states.
Innovation Solution
A field-effect transistor design with a semiconductor layer where the source and drain terminals are on one side and the gate is on the opposite side, allowing for electrostatic doping of common regions to induce a channel, reducing the need for spacer distance and enabling dynamic control of doping levels to optimize drive current and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length L is scaled down to increase transistor density, then the transistor footprint area is reduced, but short-channel effects increase causing subthreshold slope degradation and increased off-state leakage current
Solution Approach 1:
The patent transitions from a planar single-gate structure to a 3D multi-gate configuration where the gate wraps around the channel in multiple dimensions. This vertical and lateral wrapping provides enhanced electrostatic control over the channel, allowing for smaller gate lengths without suffering from short-channel effects, thus resolving the contradiction between scaling down area and maintaining reliability.
Solution Approach 2:
The patent employs a multi-layer semiconductor structure with different materials having varying bandgaps and carrier concentrations. By combining materials with different properties in the channel and barrier regions, the device achieves better electrostatic control and reduced leakage current, enabling further scaling while maintaining reliability.
2Reliability
If the channel thickness ts is reduced to improve electrostatic control, then the subthreshold slope is improved, but the drive current is reduced due to lower charge carrier concentration
Solution Approach 1:
The patent implements spatially varying doping concentrations and material compositions within the channel structure. By creating regions with different local properties (higher doping near contacts for drive current, thinner effective channel for electrostatic control), the device simultaneously achieves both improved subthreshold slope and maintained drive current.
Solution Approach 2:
The patent employs a nested structure where a thin-channel core region is surrounded by additional semiconductor layers or gates. This nested configuration provides enhanced electrostatic control from the inner thin region while the outer layers contribute to charge carrier concentration and drive current, resolving the contradiction between the two parameters.
3Area of moving object
If the spacer distance LS between terminals is reduced to increase device density, then the transistor footprint is reduced, but the electrical separation between terminals is insufficient leading to interference
Solution Approach 1:
The patent utilizes vertical separation and 3D terminal configurations to achieve electrical isolation between terminals in the lateral dimension. By stacking terminals at different heights or using through-silicon vias with isolation, the device reduces footprint while maintaining adequate electrical separation through the third dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for reduced dimensions while maintaining sufficient terminal separation, mitigating short-channel effects and improving drive current by dynamically controlling doping levels, thus enabling scaling beyond conventional limits.
Implementation Method 1
the gate is configured to, when the field-effect transistor is switched to an active state, induce an electrostatic doping of the first and second common regions of the semiconductor layer
Implementation Method 2
induce a channel in a channel region of the semiconductor layer, extending between the first and second common regions
Data Source
AI summary
A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.