Dynamic Flash Memory Cell Pillar Structure for Noise Reduction
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Solution Overview
Problem
Capacitorless single-transistor DRAM memory cells face issues with oscillation noise due to large capacitive coupling between the word line and the floating body, leading to erroneous reading and writing of data, and challenges in high-density and low-cost integration of memory cells and peripheral circuits on the same substrate.
Innovation Solution
A dynamic flash memory cell and SGT transistor configuration with specific semiconductor pillar structures, gate insulating layers, and gate conductor layers are used to control voltages for write, erase, and read operations, reducing capacitive coupling and increasing the threshold voltage margin between logic states, while allowing for high-density and cost-effective integration on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitorless single-transistor DRAM memory cell is used, then device integration density is improved, but oscillation noise increases due to large capacitive coupling between word line and floating body
Solution Approach 1:
The patent transitions from a planar 2D memory cell structure to a 3D vertical structure by forming the floating body as a pillar extending in the thickness direction of the substrate. This dimensional change allows the memory cell to achieve higher integration density while reducing the capacitive coupling area between the word line and floating body, thereby reducing oscillation noise.
Solution Approach 2:
The patent introduces a buried insulating layer that segments the substrate into multiple regions, electrically isolating the floating body from the substrate. This segmentation reduces the parasitic capacitance between the floating body and substrate, thereby reducing oscillation noise while maintaining high integration density.
2Device complexity
If capacitorless single-transistor DRAM memory cell is used, then device complexity is reduced, but manufacturing precision requirements increase due to voltage control challenges
Solution Approach 1:
The patent introduces a buried insulating layer as an intermediary between the floating body and substrate. This intermediary structure provides electrical isolation and enables better voltage control during write and erase operations, reducing the need for extremely precise voltage control while maintaining simple device structure.
Solution Approach 2:
The patent changes the physical parameters of the floating body by forming it as a vertical pillar with specific dimensions (diameter and height) rather than a planar structure. This parameter change affects the capacitance characteristics and voltage distribution, making voltage control more robust and less sensitive to manufacturing variations.
3Productivity
If memory cells and peripheral circuits are integrated on the same substrate, then device integration density is improved, but noise interference increases between memory cells and peripheral circuits
Solution Approach 1:
The buried insulating layer segments the substrate into isolated regions, creating electrical barriers between memory cells and peripheral circuits. This segmentation reduces noise interference while allowing both memory cells and peripheral circuits to be integrated on the same substrate at high density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces noise-induced errors and enhances the operational margin of the dynamic flash memory cell, enabling reliable data storage and high-density integration of memory cells and peripheral circuits on the same substrate.
Implementation Method 1
the dynamic flash memory cell is configured to perform an operation of generating an electron group and a hole group in the first semiconductor pillar by causing an impact ionization phenomenon using a current flowing between the first impurity layer and the second impurity layer
Implementation Method 2
Capacitorless single-transistor DRAM memory cells face issues with oscillation noise due to large capacitive coupling between the word line and the floating body
Data Source
AI summary
In a dynamic flash memory cell including: a HfO2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate; a HfO2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N+ layers connected to a bottom portion and a top portion of the Si pillar, and an SGT transistor including: a SiO2 layer surrounding a lower portion of a Si pillar standing on the same P-layer substrate; a HfO2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N+ layers sandwiching the HfO2 layer in a perpendicular direction and connected to a top portion and a middle portion of the Si pillar, bottom positions of the Si pillar and the Si pillar are at the same position A. A bottom portion of an upper transistor portion of the dynamic flash memory cell composed of the HfO2 layer and the TiN layer in an upper portion of the Si pillar, and a bottom portion of an SGT transistor portion composed of the HfO2 layer and the TiN layer in an upper portion of the Si pillar are at the same position B.